From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Jul 2022 10:41:04 +0000 (+0100)
Subject: clarify
X-Git-Tag: opf_rfc_ls005_v1~979
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c89148fc2bf01c0906aa6e5a43d5dae482186739;p=libreriscv.git

clarify
---

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index d0c7e8057..712ad7f16 100644
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -10,7 +10,7 @@
 |RVV (18)      |~190 (19)      |~25000 (30)       |Scalable (20)        |yes                |yes                 |no                   |yes                      |yes (21)        |no      |yes                  |no                            |no                   |no                   |
 |Aurora SX(22) |~200 (23)      |unknown (31)      |Scalable (24)        |yes                |yes                 |no                   |yes                      |no              |no      |no                   |no                            |no                   |no                   |
 
-* (1): plus EXT001 24-bit prefixing. See [[sv/svp64]]
+* (1): plus EXT001 24-bit prefixing using 25% of EXT001 space. See [[sv/svp64]]
 * (2): A 2-Dimensional Scalable Vector ISA **specifically designed for the Power ISA** with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]]
 * (3): on specific operations.  See [[opcode_regs_deduped]] for full list. Key: 2P - Twin Predication, 1P - Single-Predicate
 * (4): SVP64 provides a Vector concept on top of the **Scalar** GPR, FPR and CR Fields, extended to 128 entries.