From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 18 Sep 2015 08:01:08 +0000 (+0200)
Subject: Added $finish and $display to README
X-Git-Tag: yosys-0.6~162
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c89ceee219b5a6412a64f585caeceb5db9528fe4;p=yosys.git

Added $finish and $display to README
---

diff --git a/README b/README
index 0a1c20688..868fd90e1 100644
--- a/README
+++ b/README
@@ -367,6 +367,10 @@ Verilog Attributes and non-standard features
   expressions as <size>. If the expression is not a simple identifier, it
   must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010
 
+- The system tasks $finish and $display are supported in initial blocks
+  in and unconditional context (only if/case statements on parameters
+  and constant values). The intended use for this is synthesis-time DRC.
+
 
 Supported features from SystemVerilog
 =====================================