From: Luke Kenneth Casson Leighton Date: Fri, 6 Apr 2018 16:56:38 +0000 (+0100) Subject: partial update X-Git-Tag: convert-csv-opcode-to-binary~5744 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8a9413fb8f4535f9b7a19076bcc2a6452dca48a;p=libreriscv.git partial update --- diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index c592a598c..134d98579 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -111,6 +111,15 @@ to keep ALU pipelines 100% occupied. This very simple proposal offers a way to increase pipeline activity in the one key area which really matters: the inner loop. +## Mask and Tagging + +*TODO: research masks as they can be superb and extremely powerful. +If B-Extension is implemented and provides Bit-Gather-Scatter it +becomes really cool and easy to switch out certain indexed values +from an array of data, but actually BGS **on its own** might be +sufficient. Bottom line, this is complex, and needs a proper analysis. +The other sections are pretty straightforward.* + ## Conclusions In the above sections the four different ways where parallel instruction @@ -122,6 +131,7 @@ follows: * Implicit (indirect) vs fixed (integral) instruction bit-width: indirect * Implicit vs explicit type-conversion: explicit * Implicit vs explicit inner loops: implicit +* Tag or no-tag: TODO In particular: variable-length vectors came out on top because of the high setup, teardown and corner-cases associated with the fixed width @@ -131,6 +141,9 @@ and implicit (zero-overhead) loops provide a means to keep pipelines potentially 100% occupied *without* requiring a super-scalar or out-of-order architecture. +Constructing a SIMD/Simple-Vector proposal based around even only these four +(five?) requirements would therefore seem to be a logical thing to do. + # References * SIMD considered harmful