From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 20 Apr 2021 14:37:24 +0000 (+0100)
Subject: use soc.bus.sram instead of nmigen_soc.wishbone.sram
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8ad3d01dff5b258ac72d96e91ea6ebc478e5505;p=soc.git

use soc.bus.sram instead of nmigen_soc.wishbone.sram
---

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
index 9e34add2..4e59437e 100644
--- a/src/soc/bus/test/test_minerva.py
+++ b/src/soc/bus/test/test_minerva.py
@@ -1,4 +1,4 @@
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 from soc.minerva.units.loadstore import BareLoadStoreUnit, CachedLoadStoreUnit
 from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit
diff --git a/src/soc/bus/test/test_sram_wb_downconvert.py b/src/soc/bus/test/test_sram_wb_downconvert.py
index fe87bf49..7b5a5e9d 100644
--- a/src/soc/bus/test/test_sram_wb_downconvert.py
+++ b/src/soc/bus/test/test_sram_wb_downconvert.py
@@ -1,7 +1,7 @@
 """demonstration of nmigen-soc SRAM behind a wishbone bus and a downconverter
 """
 from nmigen_soc.wishbone.bus import Interface
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 from nmigen.utils import log2_int
 from soc.bus.wb_downconvert import WishboneDownConvert
diff --git a/src/soc/bus/test/test_sram_wishbone.py b/src/soc/bus/test/test_sram_wishbone.py
index 05ecc202..6011845d 100644
--- a/src/soc/bus/test/test_sram_wishbone.py
+++ b/src/soc/bus/test/test_sram_wishbone.py
@@ -2,7 +2,7 @@
 Bugs:
 * https://bugs.libre-soc.org/show_bug.cgi?id=382
 """
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 
 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
diff --git a/src/soc/debug/dmi2jtag.py b/src/soc/debug/dmi2jtag.py
index bc32f580..50b21166 100644
--- a/src/soc/debug/dmi2jtag.py
+++ b/src/soc/debug/dmi2jtag.py
@@ -7,7 +7,7 @@ from nmigen import (Module, Signal, Elaboratable, Const)
 from nmigen.cli import rtlil
 from c4m.nmigen.jtag.tap import TAP, IOType
 
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 
 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
diff --git a/src/soc/debug/firmware_upload.py b/src/soc/debug/firmware_upload.py
index e0e16867..053b3860 100644
--- a/src/soc/debug/firmware_upload.py
+++ b/src/soc/debug/firmware_upload.py
@@ -13,7 +13,7 @@ from soc.debug.test.dmi_sim import dmi_sim
 from soc.debug.jtag import JTAG
 from soc.debug.test.jtagremote import JTAGServer, JTAGClient
 
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 
 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
diff --git a/src/soc/debug/test/test_jtag_tap.py b/src/soc/debug/test/test_jtag_tap.py
index 757c313c..528aa34a 100644
--- a/src/soc/debug/test/test_jtag_tap.py
+++ b/src/soc/debug/test/test_jtag_tap.py
@@ -9,7 +9,7 @@ from soc.debug.dmi import DMIInterface, DBGCore
 from soc.debug.test.dmi_sim import dmi_sim
 from soc.debug.dmi2jtag import DMITAP
 
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 
 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
diff --git a/src/soc/debug/test/test_jtag_tap_srv.py b/src/soc/debug/test/test_jtag_tap_srv.py
index cbc25463..a7214575 100644
--- a/src/soc/debug/test/test_jtag_tap_srv.py
+++ b/src/soc/debug/test/test_jtag_tap_srv.py
@@ -12,7 +12,7 @@ from soc.debug.test.dmi_sim import dmi_sim
 from soc.debug.jtag import JTAG
 from soc.debug.test.jtagremote import JTAGServer, JTAGClient
 
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory, Signal, Module
 
 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index e1f82b77..959bff56 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -30,7 +30,7 @@ from soc.experiment.cache_ram import CacheRam
 from nmutil.plru import PLRU
 
 # for test
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory
 from nmigen.cli import rtlil
 
diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 732245c1..1b8aa858 100644
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -41,7 +41,7 @@ from soc.experiment.wb_types import (WB_ADDR_BITS, WB_DATA_BITS,
                                      WBIOMasterOut, WBIOSlaveOut)
 
 # for test
-from nmigen_soc.wishbone.sram import SRAM
+from soc.bus.sram import SRAM
 from nmigen import Memory
 from nmutil.util import wrap
 from nmigen.cli import main, rtlil