From: Topi Pohjolainen Date: Tue, 17 Mar 2015 11:09:16 +0000 (+0200) Subject: i965: Refactor rb surface setup to allow caller to store offsets X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8b0d890c0b7e6aa5ed326b94ac30dcb7278e7ea;p=mesa.git i965: Refactor rb surface setup to allow caller to store offsets Notice that in gen7_wm_surface_state.c there is also indentation change in the surrounding code removing tabs. v2 (Matt): Fixed whitespace: tabs -> spaces Reviewed-by: Kenneth Graunke Reviewed-by: Matt Turner Signed-off-by: Topi Pohjolainen --- diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 8db1028d9fb..e2f26f5b2d4 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -967,10 +967,10 @@ struct brw_context unsigned unit, uint32_t *surf_offset, bool for_gather); - void (*update_renderbuffer_surface)(struct brw_context *brw, - struct gl_renderbuffer *rb, - bool layered, - unsigned unit); + uint32_t (*update_renderbuffer_surface)(struct brw_context *brw, + struct gl_renderbuffer *rb, + bool layered, unsigned unit, + uint32_t surf_index); void (*emit_texture_surface_state)(struct brw_context *brw, struct intel_mipmap_tree *mt, diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 161d140a3df..d4519400f83 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -626,11 +626,11 @@ brw_emit_null_surface_state(struct brw_context *brw, * While it is only used for the front/back buffer currently, it should be * usable for further buffers when doing ARB_draw_buffer support. */ -static void +static uint32_t brw_update_renderbuffer_surface(struct brw_context *brw, - struct gl_renderbuffer *rb, - bool layered, - unsigned int unit) + struct gl_renderbuffer *rb, + bool layered, unsigned unit, + uint32_t surf_index) { struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); @@ -638,11 +638,10 @@ brw_update_renderbuffer_surface(struct brw_context *brw, uint32_t *surf; uint32_t tile_x, tile_y; uint32_t format = 0; + uint32_t offset; /* _NEW_BUFFERS */ mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); /* BRW_NEW_FS_PROG_DATA */ - uint32_t surf_index = - brw->wm.prog_data->binding_table.render_target_start + unit; assert(!layered); @@ -663,8 +662,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, intel_miptree_used_for_rendering(irb->mt); - surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, - &brw->wm.base.surf_offset[surf_index]); + surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset); format = brw->render_target_format[rb_format]; if (unlikely(!brw->format_supported_as_render_target[rb_format])) { @@ -721,11 +719,13 @@ brw_update_renderbuffer_surface(struct brw_context *brw, } drm_intel_bo_emit_reloc(brw->batch.bo, - brw->wm.base.surf_offset[surf_index] + 4, - mt->bo, - surf[1] - mt->bo->offset64, - I915_GEM_DOMAIN_RENDER, - I915_GEM_DOMAIN_RENDER); + offset + 4, + mt->bo, + surf[1] - mt->bo->offset64, + I915_GEM_DOMAIN_RENDER, + I915_GEM_DOMAIN_RENDER); + + return offset; } /** @@ -743,13 +743,15 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw) /* Update surfaces for drawing buffers */ if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) { for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { + const uint32_t surf_index = + brw->wm.prog_data->binding_table.render_target_start + i; + if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) { - brw->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], - ctx->DrawBuffer->MaxNumLayers > 0, i); + brw->wm.base.surf_offset[surf_index] = + brw->vtbl.update_renderbuffer_surface( + brw, ctx->DrawBuffer->_ColorDrawBuffers[i], + ctx->DrawBuffer->MaxNumLayers > 0, i, surf_index); } else { - const uint32_t surf_index = - brw->wm.prog_data->binding_table.render_target_start + i; - brw->vtbl.emit_null_surface_state( brw, fb->Width, fb->Height, fb->Visual.samples, &brw->wm.base.surf_offset[surf_index]); diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c b/src/mesa/drivers/dri/i965/gen6_surface_state.c index fadc3530978..03e913a0a76 100644 --- a/src/mesa/drivers/dri/i965/gen6_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen6_surface_state.c @@ -45,17 +45,18 @@ * While it is only used for the front/back buffer currently, it should be * usable for further buffers when doing ARB_draw_buffer support. */ -static void +static uint32_t gen6_update_renderbuffer_surface(struct brw_context *brw, struct gl_renderbuffer *rb, - bool layered, - unsigned int unit) + bool layered, unsigned unit /* unused */, + uint32_t surf_index) { struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); struct intel_mipmap_tree *mt = irb->mt; uint32_t *surf; uint32_t format = 0; + uint32_t offset; /* _NEW_BUFFERS */ mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); uint32_t surftype; @@ -63,13 +64,9 @@ gen6_update_renderbuffer_surface(struct brw_context *brw, const GLenum gl_target = rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D; - uint32_t surf_index = - brw->wm.prog_data->binding_table.render_target_start + unit; - intel_miptree_used_for_rendering(irb->mt); - surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, - &brw->wm.base.surf_offset[surf_index]); + surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset); format = brw->render_target_format[rb_format]; if (unlikely(!brw->format_supported_as_render_target[rb_format])) { @@ -131,11 +128,13 @@ gen6_update_renderbuffer_surface(struct brw_context *brw, surf[5] = (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0); drm_intel_bo_emit_reloc(brw->batch.bo, - brw->wm.base.surf_offset[surf_index] + 4, - mt->bo, - surf[1] - mt->bo->offset64, - I915_GEM_DOMAIN_RENDER, - I915_GEM_DOMAIN_RENDER); + offset + 4, + mt->bo, + surf[1] - mt->bo->offset64, + I915_GEM_DOMAIN_RENDER, + I915_GEM_DOMAIN_RENDER); + + return offset; } void diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 4b8503c8ccb..15ab2b0eae3 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -448,11 +448,11 @@ gen7_emit_null_surface_state(struct brw_context *brw, * While it is only used for the front/back buffer currently, it should be * usable for further buffers when doing ARB_draw_buffer support. */ -static void +static uint32_t gen7_update_renderbuffer_surface(struct brw_context *brw, - struct gl_renderbuffer *rb, - bool layered, - unsigned int unit) + struct gl_renderbuffer *rb, + bool layered, unsigned unit /* unused */, + uint32_t surf_index) { struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); @@ -464,17 +464,15 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, bool is_array = false; int depth = MAX2(irb->layer_count, 1); const uint8_t mocs = GEN7_MOCS_L3; + uint32_t offset; int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1); GLenum gl_target = rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D; - uint32_t surf_index = - brw->wm.prog_data->binding_table.render_target_start + unit; - uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, - &brw->wm.base.surf_offset[surf_index]); + &offset); memset(surf, 0, 8 * 4); intel_miptree_used_for_rendering(irb->mt); @@ -539,7 +537,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT; if (irb->mt->mcs_mt) { - gen7_set_surface_mcs_info(brw, surf, brw->wm.base.surf_offset[surf_index], + gen7_set_surface_mcs_info(brw, surf, offset, irb->mt->mcs_mt, true /* is RT */); } @@ -553,13 +551,15 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, } drm_intel_bo_emit_reloc(brw->batch.bo, - brw->wm.base.surf_offset[surf_index] + 4, - mt->bo, - surf[1] - mt->bo->offset64, - I915_GEM_DOMAIN_RENDER, - I915_GEM_DOMAIN_RENDER); + offset + 4, + mt->bo, + surf[1] - mt->bo->offset64, + I915_GEM_DOMAIN_RENDER, + I915_GEM_DOMAIN_RENDER); gen7_check_surface_setup(surf, true /* is_render_target */); + + return offset; } void diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index f347065d102..d0c2d80b17b 100644 --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c @@ -324,11 +324,11 @@ gen8_emit_null_surface_state(struct brw_context *brw, * While it is only used for the front/back buffer currently, it should be * usable for further buffers when doing ARB_draw_buffer support. */ -static void +static uint32_t gen8_update_renderbuffer_surface(struct brw_context *brw, struct gl_renderbuffer *rb, - bool layered, - unsigned unit) + bool layered, unsigned unit /* unused */, + uint32_t surf_index) { struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); @@ -341,14 +341,13 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, uint32_t tiling = mt->tiling; uint32_t format = 0; uint32_t surf_type; + uint32_t offset; bool is_array = false; int depth = MAX2(irb->layer_count, 1); const int min_array_element = (mt->format == MESA_FORMAT_S_UINT8) ? irb->mt_layer : (irb->mt_layer / MAX2(mt->num_samples, 1)); GLenum gl_target = rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D; - uint32_t surf_index = - brw->wm.prog_data->binding_table.render_target_start + unit; /* FINISHME: Use PTE MOCS on Skylake. */ uint32_t mocs = brw->gen >= 9 ? SKL_MOCS_WT : BDW_MOCS_PTE; @@ -393,8 +392,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, aux_mode = GEN8_SURFACE_AUX_MODE_MCS; } - uint32_t *surf = - allocate_surface_state(brw, &brw->wm.base.surf_offset[surf_index]); + uint32_t *surf = allocate_surface_state(brw, &offset); surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) | (is_array ? GEN7_SURFACE_IS_ARRAY : 0) | @@ -439,7 +437,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, if (aux_mt) { *((uint64_t *) &surf[10]) = aux_mt->bo->offset64; drm_intel_bo_emit_reloc(brw->batch.bo, - brw->wm.base.surf_offset[surf_index] + 10 * 4, + offset + 10 * 4, aux_mt->bo, 0, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); } else { @@ -449,11 +447,13 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, surf[12] = 0; drm_intel_bo_emit_reloc(brw->batch.bo, - brw->wm.base.surf_offset[surf_index] + 8 * 4, + offset + 8 * 4, mt->bo, mt->offset, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); + + return offset; } void