From: Christian Bruel Date: Tue, 15 Sep 2015 13:43:17 +0000 (+0200) Subject: re PR target/52144 (ARM should support arm/thumb function attribute to permit differe... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8b6aa7c12ab17f947bba5295d010f6f05be2383;p=gcc.git re PR target/52144 (ARM should support arm/thumb function attribute to permit different instruction sets in the same source) 2015-09-15 Christian Bruel PR target/52144 * config/arm/arm.c (arm_option_params_internal): Remove opts parameter. * config/arm/arm-c.c (arm_cpu_builtins): Declare static. Remove flags parameter. * config/arm/arm.h (TARGET_32BIT_P, TARGET_ARM_QBIT_P) (TARGET_ARM_SAT_P, TARGET_IDIV_P, TARGET_HAVE_LDREX_P) (TARGET_HAVE_LDREXBH_P, TARGET_HAVE_LDREXD_P, TARGET_DSP_MULTIPLY_P) (TARGET_ARM_FEATURE_LDREX_P, TARGET_INT_SIMD_P): Redefine macros with... (TARGET_ARM_SAT, TARGET_IDIV, TARGET_HAVE_LDREX) (TARGET_HAVE_LDREXBH, TARGET_HAVE_LDREXD, TARGET_ARM_FEATURE_LDREX) (TARGET_DSP_MULTIPLY, TARGET_INT_SIMD): Redefined macros. * gcc/config/arm/arm-protos.h (arm_cpu_builtins): Remove declaration. From-SVN: r227795 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 38719b9e03a..72de7ff9f61 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2015-09-15 Christian Bruel + + PR target/52144 + * config/arm/arm.c (arm_option_params_internal): Remove opts parameter. + * config/arm/arm-c.c (arm_cpu_builtins): Declare static. + Remove flags parameter. + * config/arm/arm.h (TARGET_32BIT_P, TARGET_ARM_QBIT_P) + (TARGET_ARM_SAT_P, TARGET_IDIV_P, TARGET_HAVE_LDREX_P) + (TARGET_HAVE_LDREXBH_P, TARGET_HAVE_LDREXD_P, TARGET_DSP_MULTIPLY_P) + (TARGET_ARM_FEATURE_LDREX_P, TARGET_INT_SIMD_P): Redefine macros with: + (TARGET_ARM_SAT, TARGET_IDIV, TARGET_HAVE_LDREX) + (TARGET_HAVE_LDREXBH, TARGET_HAVE_LDREXD, TARGET_ARM_FEATURE_LDREX) + (TARGET_DSP_MULTIPLY, TARGET_INT_SIMD): Redefined macros. + * gcc/config/arm/arm-protos.h (arm_cpu_builtins): Remove declaration. + 2015-09-15 Alan Lawrence * config/aarch64/aarch64.h (AARCH64_VALID_SIMD_DREG_MODE): New. diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c index 9bf3973f290..4754a15f52c 100644 --- a/gcc/config/arm/arm-c.c +++ b/gcc/config/arm/arm-c.c @@ -54,23 +54,20 @@ arm_lang_object_attributes_init (void) #pragma GCC target, we need to adjust the macros dynamically. */ static void -def_or_undef_macro(struct cpp_reader* pfile, const char *name, bool def_p) +def_or_undef_macro(struct cpp_reader* pfile, const char *name, bool def_p) { if (def_p) - cpp_define (pfile, name); - else - cpp_undef (pfile, name); -} + cpp_define (pfile, name); + else + cpp_undef (pfile, name); +} -void -arm_cpu_builtins (struct cpp_reader* pfile, int flags) +static void +arm_cpu_builtins (struct cpp_reader* pfile) { - def_or_undef_macro (pfile, "__ARM_FEATURE_DSP", - TARGET_DSP_MULTIPLY_P (flags)); - def_or_undef_macro (pfile, "__ARM_FEATURE_QBIT", - TARGET_ARM_QBIT_P (flags)); - def_or_undef_macro (pfile, "__ARM_FEATURE_SAT", - TARGET_ARM_SAT_P (flags)); + def_or_undef_macro (pfile, "__ARM_FEATURE_DSP", TARGET_DSP_MULTIPLY); + def_or_undef_macro (pfile, "__ARM_FEATURE_QBIT", TARGET_ARM_QBIT); + def_or_undef_macro (pfile, "__ARM_FEATURE_SAT", TARGET_ARM_SAT); if (TARGET_CRYPTO) builtin_define ("__ARM_FEATURE_CRYPTO"); if (unaligned_access) @@ -78,19 +75,19 @@ arm_cpu_builtins (struct cpp_reader* pfile, int flags) if (TARGET_CRC32) builtin_define ("__ARM_FEATURE_CRC32"); - def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT_P (flags)); + def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT); - if (TARGET_ARM_FEATURE_LDREX_P (flags)) + if (TARGET_ARM_FEATURE_LDREX) builtin_define_with_int_value ("__ARM_FEATURE_LDREX", - TARGET_ARM_FEATURE_LDREX_P (flags)); + TARGET_ARM_FEATURE_LDREX); else cpp_undef (pfile, "__ARM_FEATURE_LDREX"); def_or_undef_macro (pfile, "__ARM_FEATURE_CLZ", - ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB_P (flags)) + ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) || TARGET_ARM_ARCH_ISA_THUMB >=2)); - def_or_undef_macro (pfile, "__ARM_FEATURE_SIMD32", TARGET_INT_SIMD_P (flags)); + def_or_undef_macro (pfile, "__ARM_FEATURE_SIMD32", TARGET_INT_SIMD); builtin_define_with_int_value ("__ARM_SIZEOF_MINIMAL_ENUM", flag_short_enums ? 1 : 4); @@ -108,12 +105,12 @@ arm_cpu_builtins (struct cpp_reader* pfile, int flags) builtin_define ("__ARM_ARCH_ISA_ARM"); builtin_define ("__APCS_32__"); - def_or_undef_macro (pfile, "__thumb__", TARGET_THUMB_P (flags)); - def_or_undef_macro (pfile, "__thumb2__", TARGET_THUMB2_P (flags)); + def_or_undef_macro (pfile, "__thumb__", TARGET_THUMB); + def_or_undef_macro (pfile, "__thumb2__", TARGET_THUMB2); if (TARGET_BIG_END) - def_or_undef_macro (pfile, "__THUMBEB__", TARGET_THUMB_P (flags)); + def_or_undef_macro (pfile, "__THUMBEB__", TARGET_THUMB); else - def_or_undef_macro (pfile, "__THUMBEL__", TARGET_THUMB_P (flags)); + def_or_undef_macro (pfile, "__THUMBEL__", TARGET_THUMB); if (TARGET_ARM_ARCH_ISA_THUMB) builtin_define_with_int_value ("__ARM_ARCH_ISA_THUMB", @@ -181,8 +178,8 @@ arm_cpu_builtins (struct cpp_reader* pfile, int flags) builtin_define ("__ARM_EABI__"); } - def_or_undef_macro (pfile, "__ARM_ARCH_EXT_IDIV__", TARGET_IDIV_P (flags)); - def_or_undef_macro (pfile, "__ARM_FEATURE_IDIV", TARGET_IDIV_P (flags)); + def_or_undef_macro (pfile, "__ARM_ARCH_EXT_IDIV__", TARGET_IDIV); + def_or_undef_macro (pfile, "__ARM_FEATURE_IDIV", TARGET_IDIV); def_or_undef_macro (pfile, "__ARM_ASM_SYNTAX_UNIFIED__", inline_asm_unified); } @@ -193,7 +190,7 @@ arm_cpu_cpp_builtins (struct cpp_reader * pfile) builtin_assert ("cpu=arm"); builtin_assert ("machine=arm"); - arm_cpu_builtins (pfile, target_flags); + arm_cpu_builtins (pfile); } /* Hook to validate the current #pragma GCC target and set the arch custom @@ -245,7 +242,8 @@ arm_pragma_target_parse (tree args, tree pop_target) cpp_opts->warn_unused_macros = 0; /* Update macros. */ - arm_cpu_builtins (parse_in, cur_opt->x_target_flags); + gcc_assert (cur_opt->x_target_flags == target_flags); + arm_cpu_builtins (parse_in); cpp_opts->warn_unused_macros = saved_warn_unused_macros; } diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 8df312f3c67..d3d7216488e 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -340,7 +340,6 @@ extern const char *arm_rewrite_selected_cpu (const char *name); extern void arm_lang_object_attributes_init (void); extern void arm_register_target_pragmas (void); extern void arm_cpu_cpp_builtins (struct cpp_reader *); -extern void arm_cpu_builtins (struct cpp_reader *, int); extern bool arm_is_constant_pool_ref (rtx); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 5f3180d38ce..214d0b15789 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2751,15 +2751,14 @@ arm_option_check_internal (struct gcc_options *opts) error ("-mslow-flash-data only supports non-pic code on armv7-m targets"); } -/* Set params depending on attributes and optimization options. */ +/* Recompute the global settings depending on target attribute options. */ + static void -arm_option_params_internal (struct gcc_options *opts) +arm_option_params_internal (void) { - int flags = opts->x_target_flags; - - /* If we are not using the default (ARM mode) section anchor offset + /* If we are not using the default (ARM mode) section anchor offset ranges, then set the correct ranges now. */ - if (TARGET_THUMB1_P (flags)) + if (TARGET_THUMB1) { /* Thumb-1 LDR instructions cannot have negative offsets. Permissible positive offset ranges are 5-bit (for byte loads), @@ -2769,7 +2768,7 @@ arm_option_params_internal (struct gcc_options *opts) targetm.min_anchor_offset = 0; targetm.max_anchor_offset = 127; } - else if (TARGET_THUMB2_P (flags)) + else if (TARGET_THUMB2) { /* The minimum is set such that the total size of the block for a particular anchor is 248 + 1 + 4095 bytes, which is @@ -2790,14 +2789,13 @@ arm_option_params_internal (struct gcc_options *opts) max_insns_skipped = 6; /* For THUMB2, we limit the conditional sequence to one IT block. */ - if (TARGET_THUMB2_P (flags)) - max_insns_skipped = opts->x_arm_restrict_it ? 1 : 4; + if (TARGET_THUMB2) + max_insns_skipped = arm_restrict_it ? 1 : 4; } else /* When -mrestrict-it is in use tone down the if-conversion. */ - max_insns_skipped - = (TARGET_THUMB2_P (opts->x_target_flags) && opts->x_arm_restrict_it) - ? 1 : current_tune->max_insns_skipped; + max_insns_skipped = (TARGET_THUMB2 && arm_restrict_it) + ? 1 : current_tune->max_insns_skipped; } /* True if -mflip-thumb should next add an attribute for the default @@ -3385,7 +3383,7 @@ arm_option_override (void) arm_option_override_internal (&global_options, &global_options_set); arm_option_check_internal (&global_options); - arm_option_params_internal (&global_options); + arm_option_params_internal (); /* Register global variables with the garbage collector. */ arm_add_gc_roots (); @@ -29482,7 +29480,7 @@ arm_set_current_function (tree fndecl) = save_target_globals_default_opts (); } - arm_option_params_internal (&global_options); + arm_option_params_internal (); } /* Hook to determine if one function can safely inline another. */ @@ -29501,7 +29499,7 @@ arm_can_inline_p (tree caller ATTRIBUTE_UNUSED, tree callee ATTRIBUTE_UNUSED) go over the list. */ static bool -arm_valid_target_attribute_rec (tree args, struct gcc_options *opts) +arm_valid_target_attribute_rec (tree args, struct gcc_options *opts) { if (TREE_CODE (args) == TREE_LIST) { diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index f7a9d638673..87c9f904894 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -160,8 +160,6 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) /* Arm or Thumb-2 32-bit code. */ #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) -#define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) \ - || arm_arch_thumb2) /* 32-bit Thumb-2 code. */ #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) /* Thumb-1 only. */ @@ -220,23 +218,18 @@ extern void (*arm_lang_output_object_attributes_hook)(void); (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP \ && ARM_FPU_FSET_HAS (arm_fpu_desc->features, FPU_FL_NEON)) - /* Q-bit is present. */ -#define TARGET_ARM_QBIT_P(flags) \ - (TARGET_32BIT_P (flags) && arm_arch5e && (arm_arch_notm || arm_arch7)) -#define TARGET_ARM_QBIT TARGET_ARM_QBIT_P(target_flags) +#define TARGET_ARM_QBIT \ + (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7)) /* Saturation operation, e.g. SSAT. */ -#define TARGET_ARM_SAT_P(flags) \ - (TARGET_32BIT_P (flags) && arm_arch6 && (arm_arch_notm || arm_arch7)) -#define TARGET_ARM_SAT TARGET_ARM_SAT_P(target_flags) +#define TARGET_ARM_SAT \ + (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) /* "DSP" multiply instructions, eg. SMULxy. */ -#define TARGET_DSP_MULTIPLY_P(flags) \ - (TARGET_32BIT_P (flags) && arm_arch5e && (arm_arch_notm || arm_arch7em)) -#define TARGET_DSP_MULTIPLY TARGET_DSP_MULTIPLY_P(target_flags) +#define TARGET_DSP_MULTIPLY \ + (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) /* Integer SIMD instructions, and extend-accumulate instructions. */ -#define TARGET_INT_SIMD_P(flags) \ - (TARGET_32BIT_P (flags) && arm_arch6 && (arm_arch_notm || arm_arch7em)) -#define TARGET_INT_SIMD TARGET_INT_SIMD_P(target_flags) +#define TARGET_INT_SIMD \ + (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) /* Should MOVW/MOVT be used in preference to a constant pool. */ #define TARGET_USE_MOVT \ @@ -259,30 +252,21 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) /* Nonzero if this chip supports ldrex and strex */ -#define TARGET_HAVE_LDREX_P(flags) ((arm_arch6 && TARGET_ARM_P (flags)) \ - || arm_arch7) -#define TARGET_HAVE_LDREX TARGET_HAVE_LDREX_P (target_flags) +#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ -#define TARGET_HAVE_LDREXBH_P(flags) ((arm_arch6k && TARGET_ARM_P (flags)) \ - || arm_arch7) -#define TARGET_HAVE_LDREXBH TARGET_HAVE_LDREXBH_P (target_flags) +#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) /* Nonzero if this chip supports ldrexd and strexd. */ -#define TARGET_HAVE_LDREXD_P(flags) (((arm_arch6k && TARGET_ARM_P (flags)) \ - || arm_arch7) && arm_arch_notm) -#define TARGET_HAVE_LDREXD TARGET_HAVE_LDREXD_P (target_flags) - +#define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ + || arm_arch7) && arm_arch_notm) /* Nonzero if this chip supports load-acquire and store-release. */ #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) /* Nonzero if integer division instructions supported. */ -#define TARGET_IDIV_P(flags) ((TARGET_ARM_P (flags) && arm_arch_arm_hwdiv) \ - || (TARGET_THUMB2_P (flags) \ - && arm_arch_thumb_hwdiv)) -#define TARGET_IDIV TARGET_IDIV_P (target_flags) - +#define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ + || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) /* Nonzero if disallow volatile memory access in IT block. */ #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) @@ -2220,11 +2204,6 @@ extern int making_const_table; | (TARGET_HAVE_LDREXBH ? 3 : 0) \ | (TARGET_HAVE_LDREXD ? 8 : 0)) -#define TARGET_ARM_FEATURE_LDREX_P(flags) \ - ((TARGET_HAVE_LDREX_P (flags) ? 4 : 0) \ - | (TARGET_HAVE_LDREXBH_P (flags) ? 3 : 0) \ - | (TARGET_HAVE_LDREXD_P (flags) ? 8 : 0)) - /* Set as a bit mask indicating the available widths of hardware floating point types. Where bit 1 indicates 16-bit support, bit 2 indicates 32-bit support, bit 3 indicates 64-bit support. */