From: lkcl Date: Thu, 24 Dec 2020 09:13:07 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~967 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8bc4a60a323aa1c5de8bff80a171c2bd88c2751;p=libreriscv.git --- diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index ac91fdb3d..fc2d2f02d 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -75,7 +75,7 @@ With some walkthroughs it is clear that the loop exits immediately after the fir In this way all the eight permutations of Scalar and Vector behaviour are covered, although without predication the scalar-destination ones are reduced in usefulness. It does however clearly illustrate the principle. -Note in particular: there is no separate Scalar add instruction and separate Vector instruction and separate Scalar-Vector instruction: it's all the same instruction, just with a loop. Scalar happens to set that loop size to one. +Note in particular: there is no separate Scalar add instruction and separate Vector instruction and separate Scalar-Vector instruction, *and there is no separate Vector register file*: it's all the same instruction, on the standard register file, just with a loop. Scalar happens to set that loop size to one. # Adding single predication