From: lkcl <lkcl@web>
Date: Tue, 7 Jun 2022 04:14:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1925
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8bde7657913d351cf332df585184804708ee968;p=libreriscv.git

---

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index 24800cbc4..f029c08a6 100644
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -68,7 +68,7 @@ arbitrary remapping the `Indexed` REMAP may be used.
   otherwise usual `0..VL-1` hardware for-loop
 * `svremap` to set which registers a given reordering is to apply to
   (RA, RT etc)
-* `sv.instruction` where any Vectotised register marked by `svremap`
+* `sv.instruction` where any Vectorised register marked by `svremap`
   will have its ordering REMAPPED according to the schedule set
   by `svshape`.