From: lkcl <lkcl@web>
Date: Sun, 3 Apr 2022 15:08:44 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2899
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8bfba7a93ec76d9bd36f15003430437e778fe7b;p=libreriscv.git

---

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index afb375d0c..16f8d4c0d 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -114,8 +114,9 @@ dest elwidth.
 Reduction in SVP64 is similar in essence to other Vector Processing
 ISAs, but leverages the underlying scalar Base v3.0B operations.
 Thus it is more a convention that the programmer may utilise to give
-the appearance and effect of a Horizontal Vector Reduction.
-Details are in the [[svp64/appendix]]
+the appearance and effect of a Horizontal Vector Reduction. Due
+to the unusual decoupling it is also possible to perform
+prefix-sum in certain circumstances. Details are in the [[svp64/appendix]]
 
 # Fail-on-first