From: Mike Frysinger <vapier@gentoo.org>
Date: Sun, 28 Nov 2021 05:23:16 +0000 (-0500)
Subject: sim: riscv: switch to new target-newlib-syscall
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8c6ef3807554a17d4518e45f91c53d17a71c083;p=binutils-gdb.git

sim: riscv: switch to new target-newlib-syscall

Use the new target-newlib-syscall module.  This is needed to merge all
the architectures into a single build, and riscv has a custom syscall
table for its newlib/libgloss port.
---

diff --git a/sim/riscv/Makefile.in b/sim/riscv/Makefile.in
index 17cb288eba3..b967654d787 100644
--- a/sim/riscv/Makefile.in
+++ b/sim/riscv/Makefile.in
@@ -15,9 +15,6 @@
 # You should have received a copy of the GNU General Public License
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
-# This selects the newlib/libgloss syscall definitions.
-NL_TARGET = -DNL_TARGET_riscv
-
 ## COMMON_PRE_CONFIG_FRAG
 
 SIM_OBJS = \
diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c
index efa4b5669cb..13fe6c7cae0 100644
--- a/sim/riscv/interp.c
+++ b/sim/riscv/interp.c
@@ -24,6 +24,7 @@
 #include "sim/callback.h"
 #include "sim-main.h"
 #include "sim-options.h"
+#include "target-newlib-syscall.h"
 
 void
 sim_engine_run (SIM_DESC sd,
@@ -69,6 +70,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
   STATE_MACHS (sd) = riscv_sim_machs;
   STATE_MODEL_NAME (sd) = WITH_TARGET_WORD_BITSIZE == 32 ? "RV32G" : "RV64G";
   current_target_byte_order = BFD_ENDIAN_LITTLE;
+  callback->syscall_map = cb_riscv_syscall_map;
 
   /* The cpu data is kept in a separately allocated chunk of memory.  */
   if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)