From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Tue, 31 Mar 2015 23:07:56 +0000 (-0700)
Subject: Allow writing mstatus.fs even if FPU isn't present
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8c828b55c8e25929bdbcd00032276e04391430e;p=riscv-isa-sim.git

Allow writing mstatus.fs even if FPU isn't present

This allows the OS to track FP state dirtiness.
---

diff --git a/riscv/decode.h b/riscv/decode.h
index a1c28d5..5d304a1 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -173,7 +173,11 @@ private:
 #define require_privilege(p) if (get_field(STATE.mstatus, MSTATUS_PRV) < (p)) throw trap_illegal_instruction()
 #define require_rv64 if(unlikely(xlen != 64)) throw trap_illegal_instruction()
 #define require_rv32 if(unlikely(xlen != 32)) throw trap_illegal_instruction()
-#define require_fp if (unlikely((STATE.mstatus & MSTATUS_FS) == 0)) throw trap_illegal_instruction()
+#ifdef RISCV_ENABLE_FPU
+# define require_fp if (unlikely((STATE.mstatus & MSTATUS_FS) == 0)) throw trap_illegal_instruction()
+#else
+# define require_fp throw trap_illegal_instruction()
+#endif
 #define require_accelerator if (unlikely((STATE.mstatus & MSTATUS_XS) == 0)) throw trap_illegal_instruction()
 
 #define cmp_trunc(reg) (reg_t(reg) << (64-xlen))
diff --git a/riscv/processor.cc b/riscv/processor.cc
index afae1ce..51e56b1 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -335,10 +335,7 @@ void processor_t::set_csr(int which, reg_t val)
         mmu->flush_tlb();
 
       reg_t mask = MSTATUS_SSIP | MSTATUS_MSIP | MSTATUS_IE | MSTATUS_IE1
-                   | MSTATUS_IE2 | MSTATUS_IE3 | MSTATUS_STIE;
-#ifdef RISCV_ENABLE_FPU
-      mask |= MSTATUS_FS;
-#endif
+                   | MSTATUS_IE2 | MSTATUS_IE3 | MSTATUS_STIE | MSTATUS_FS;
       if (ext)
         mask |= MSTATUS_XS;
       state.mstatus = (state.mstatus & ~mask) | (val & mask);