From: Raptor Engineering Development Team Date: Wed, 23 Feb 2022 01:05:55 +0000 (-0600) Subject: Update Tercel README with actual core state on reset X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8e460bdabe7e88f96d42af4342b45c0b1ad485d;p=microwatt.git Update Tercel README with actual core state on reset --- diff --git a/README.tercel.md b/README.tercel.md index 874f352..96a16d1 100644 --- a/README.tercel.md +++ b/README.tercel.md @@ -10,7 +10,7 @@ Tercel provides two interfaces to the host CPU: ## General Usage -On reset, the Tercel core provides read-only access in single SPI, 3BA mode to any attached Flash device. It uses the generic well-known single byte access instructions to provide full XIP support. Host software is responsible for reading the Flash ID of the attached Flash device and reconfiguring the Tercel core for faster and more advanced operating modes. This reconfiguration can take place online, with no interruption to the concurrent read operations in progress on the main MMIO Flash window. +On reset, the Tercel core provides basic read/write access in single SPI, 3BA mode to any attached Flash device. It uses the generic well-known single byte access instructions to provide full XIP support. Host software is responsible for reading the Flash ID of the attached Flash device and reconfiguring the Tercel core for faster and more advanced operating modes. This reconfiguration can take place online, with no interruption to the concurrent read operations in progress on the main MMIO Flash window. By default, with Microwatt, the two bus regions are available at: Flash MMIO (XIP base): 0xf0000000