From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 28 Jun 2020 21:41:18 +0000 (+0100)
Subject: add cached fetch unit pass-through args
X-Git-Tag: div_pipeline~211
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8e9e6c73e1c5004485220605c90c3fe8dc4f0d4;p=soc.git

add cached fetch unit pass-through args
---

diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py
index 6b78e801..023f8909 100644
--- a/src/soc/minerva/units/fetch.py
+++ b/src/soc/minerva/units/fetch.py
@@ -75,13 +75,13 @@ class BareFetchUnit(FetchUnitInterface, Elaboratable):
 
 
 class CachedFetchUnit(FetchUnitInterface, Elaboratable):
-    def __init__(self, *icache_args):
-        super().__init__()
+    def __init__(self, *icache_args, addr_wid=32, data_wid=32):
+        super().__init__(addr_wid=addr_wid, data_wid=data_wid)
 
         self.icache_args = icache_args
 
         self.a_flush = Signal()
-        self.f_pc = Signal(32)
+        self.f_pc = Signal(addr_wid)
 
     def elaborate(self, platform):
         m = Module()