From: Pat Haugen Date: Mon, 27 Feb 2017 16:06:13 +0000 (+0000) Subject: re PR target/79544 (vec_sra (unsigned long long,foo) generating vsrd instead of vsrad) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c8f28a3c7ae87e3114e5789fd3a20e46c3a879f6;p=gcc.git re PR target/79544 (vec_sra (unsigned long long,foo) generating vsrd instead of vsrad) PR target/79544 * config/rs6000/rs6000-c.c (struct altivec_builtin_types): Use VSRAD for arithmetic shift of unsigned V2DI. * gcc.target/powerpc/pr79544.c: New. From-SVN: r245762 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 76084d81e13..9c1025dcf9e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-02-27 Pat Haugen + + PR target/79544 + * config/rs6000/rs6000-c.c (struct altivec_builtin_types): Use VSRAD + for arithmetic shift of unsigned V2DI. + 2017-02-27 Claudiu Zissulescu * config.gcc (arc*-): Clean up, use arc/big.h, arc/elf.h, and diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index b0a7d3335ee..20c17f0e787 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -2444,7 +2444,7 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRD, + { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, @@ -5012,7 +5012,7 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, - { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRD, + { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ, diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ef8980790af..55edc8a5fea 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-02-27 Pat Haugen + + PR target/79544 + * gcc.target/powerpc/pr79544.c: New. + 2017-02-27 Paolo Carlini PR c++/79414 diff --git a/gcc/testsuite/gcc.target/powerpc/pr79544.c b/gcc/testsuite/gcc.target/powerpc/pr79544.c new file mode 100644 index 00000000000..336c6d91a0c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr79544.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8 -O2" } */ + +#include + +vector unsigned long long +test_sra (vector unsigned long long x, vector unsigned long long y) +{ + return vec_sra (x, y); +} + +/* { dg-final { scan-assembler "vsrad" } } */ +