From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 7 Apr 2022 10:29:14 +0000 (+0100)
Subject: doh
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c91b473f97c9d3a28c43ab6451b206082057a24a;p=nmigen-gf.git

doh
---

diff --git a/src/nmigen_gf/hdl/cldivrem.py b/src/nmigen_gf/hdl/cldivrem.py
index 973e0c9..43257e7 100644
--- a/src/nmigen_gf/hdl/cldivrem.py
+++ b/src/nmigen_gf/hdl/cldivrem.py
@@ -98,7 +98,7 @@ class EqualLeadingZeroCount(Elaboratable):
 
         csum = Signal(self.width + 1)
         carry_in = 1  # both have no leading zeros so far, so set carry
-        m.d.comb += sum.eq(addend1 + addend2 + carry_in)
+        m.d.comb += csum.eq(addend1 + addend2 + carry_in)
         m.d.comb += self.out.eq(csum[self.width])  # out is carry-out
         return m