From: tplaten@d8aaf6947db541852330ac00af10ca032f889584 <tplaten@web>
Date: Sun, 26 Jan 2020 07:09:45 +0000 (+0000)
Subject: add link to mlabs
X-Git-Tag: convert-csv-opcode-to-binary~3701
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c91dd19c0308cc7dc8e883c7402b465998713572;p=libreriscv.git

add link to mlabs
---

diff --git a/shakti/m_class/wishbone.mdwn b/shakti/m_class/wishbone.mdwn
index 0b269e519..8af48c074 100644
--- a/shakti/m_class/wishbone.mdwn
+++ b/shakti/m_class/wishbone.mdwn
@@ -6,3 +6,5 @@ See also [[AXI]] Bus
 * <https://github.com/alexforencich/verilog-wishbone>
 * <https://github.com/qermit/WishboneAXI>
 * <https://github.com/bluecmd/wb-axi>
+* <https://github.com/m-labs/nmigen-soc>
+