From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Thu, 21 May 2020 16:35:52 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c93e8e135479cc357df372b913898763a23cae6a;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
---

diff --git a/e6/d84ef6b3b256013e07f9b2a3b9833087cf849a b/e6/d84ef6b3b256013e07f9b2a3b9833087cf849a
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+Date: Thu, 21 May 2020 16:35:52 +0000
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+X-Bugzilla-Severity: enhancement
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+Message-ID: <bug-336-13-ecAkvrNZKX@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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