From: Ian Romanick Date: Mon, 24 Oct 2016 06:47:14 +0000 (-0700) Subject: i965: Really don't emit Q or UQ moves on Gen < 8 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c95380c40;p=mesa.git i965: Really don't emit Q or UQ moves on Gen < 8 It's much easier to do this in the generator rather than while coming out of NIR. brw_type_for_nir_type doesn't know the Gen, so we'd have to add a bunch of plumbing. The alternate fix is to not emit int64 moves for doubles in the first place... but that seems even more difficult. This change won't catch non-MOV instructions that try to use 64-bit integer types on Gen < 8. This may convert certain kinds of bugs in to different kinds of bugs that are more difficult to detect (since the assertions in the function won't catch them). NOTE: I don't think anything can emit mixed-type 64-bit moves until the same platform supports both ARB_gpu_shader_fp64 and ARB_gpu_shader_int64. When we enable int64 on Gen < 8, we can solve this problem other ways. This prevents regressions on HSW in the next patch. Signed-off-by: Ian Romanick Reviewed-by: Matt Turner --- diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index cd17e3b0b0b..8d08d1856ab 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -94,6 +94,14 @@ unsigned brw_reg_type_to_hw_type(const struct gen_device_info *devinfo, enum brw_reg_type type, enum brw_reg_file file) { + /* If the type is Q or UQ and Gen < 8, change the type to DF. On Gen < 8, + * the only Q or UQ moves the should occur are actually to move doubles + * anyway. + */ + if (devinfo->gen < 8 && (type == BRW_REGISTER_TYPE_UQ || + type == BRW_REGISTER_TYPE_Q)) + type = BRW_REGISTER_TYPE_DF; + if (file == BRW_IMMEDIATE_VALUE) { static const int imm_hw_types[] = { [BRW_REGISTER_TYPE_UD] = BRW_HW_REG_TYPE_UD,