From: Sebastien Bourdeauducq Date: Thu, 12 Dec 2013 22:17:16 +0000 (+0100) Subject: gensoc: use add_verilog_include_path X-Git-Tag: 24jan2021_ls180~2751 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c95b9d6d768327224c1cff313620ee10ed8f9da7;p=litex.git gensoc: use add_verilog_include_path --- diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index 436cd4fd..615091a0 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -66,7 +66,7 @@ class GenSoC(Module): "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v", "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v", "lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v") - platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v") + platform.add_verilog_include_path(os.path.join("verilog", "lm32")) def register_rom(self, rom_wb_if, bios_size=0x8000): if self._rom_registered: