From: Dmitry Selyutin Date: Wed, 18 May 2022 19:39:22 +0000 (+0000) Subject: svp64.py: sync svshape opcode X-Git-Tag: sv_maxu_works-initial~422 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c968dab;p=openpower-isa.git svp64.py: sync svshape opcode --- diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index cebf32e4..edef3608 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -243,16 +243,16 @@ class SVP64Asm: # and svshape. note that the dimension fields one subtracted from each if opcode == 'svshape': # 1.6.33 SVM-FORM from fields.txt - # |0 |6 |11 |16 |21 |25 |26 |31 | - # |PO | SVxd | SVyd | SVzd | SVRM |vf | XO | / | + # |0 |6 |11 |16 |21 |25 |26 |31 | + # | PO | SVxd | SVyd | SVzd | SVRM |vf | XO | insn = 22 << (31-5) # opcode 22, bits 0-5 fields = list(map(int, fields)) insn |= (fields[0]-1) << (31-10) # SVxd , bits 6-10 insn |= (fields[1]-1) << (31-15) # SVyd , bits 11-15 insn |= (fields[2]-1) << (31-20) # SVzd , bits 16-20 - insn |= (fields[3]) << (31-24) # SVRM , bits 21-24 - insn |= (fields[4]) << (31-25) # vf , bits 25 - insn |= 0b00001 << (31-30) # XO , bits 26..30 + insn |= (fields[3]) << (31-24) # SVRM , bits 21-24 + insn |= (fields[4]) << (31-25) # vf , bits 25 + insn |= 0b00001 << (31-31) # XO , bits 26..31 #insn &= ((1<<32)-1) log("svshape", bin(insn)) yield ".long 0x%x" % insn