From: Clifford Wolf Date: Fri, 27 Dec 2013 14:10:07 +0000 (+0100) Subject: More $eq/$ne/$eqx/$nex fixes in opt_const X-Git-Tag: yosys-0.2.0~223 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c9699fe76deb13209d61af461d9ce850a5113c8d;p=yosys.git More $eq/$ne/$eqx/$nex fixes in opt_const --- diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index d84910ee1..a3f3ee418 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -160,6 +160,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons assert(a.chunks.size() == b.chunks.size()); for (size_t i = 0; i < a.chunks.size(); i++) { + if (a.chunks[i].wire == NULL && b.chunks[i].wire == NULL && + a.chunks[i].data.bits[0] != b.chunks[i].data.bits[0]) { + RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); + new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); + replace_cell(module, cell, "empty", "\\Y", new_y); + goto next_cell; + } if (cell->type == "$eq" || cell->type == "$ne") { if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1) continue; @@ -173,7 +180,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } if (new_a.width == 0) { - RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type == "$eq" ? RTLIL::State::S1 : RTLIL::State::S0); + RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S1 : RTLIL::State::S0); new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false); replace_cell(module, cell, "empty", "\\Y", new_y); goto next_cell;