From: Diego H <diego@yosyshq.com>
Date: Thu, 4 Feb 2021 21:35:35 +0000 (-0600)
Subject: Accept disable case for SVA liveness properties.
X-Git-Tag: working-ls180~81^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c96eb2fbd7cb2f4838350c02baf3e4b23c4b2ad2;p=yosys.git

Accept disable case for SVA liveness properties.
---

diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index 632043b6f..1f5da1b1d 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -1759,6 +1759,11 @@ struct VerificSvaImporter
 						clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0);
 					}
 
+					// accept in disable case
+
+					if (clocking.disable_sig != State::S0)
+						sig_a_q = module->Or(NEW_ID, sig_a_q, clocking.disable_sig);
+
 					// generate fair/live cell
 
 					RTLIL::Cell *c = nullptr;