From: lkcl <lkcl@web>
Date: Fri, 22 Jan 2021 14:41:43 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~388
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c97a45870c590516bfa3b022f7ad458f47a799df;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index b8230f3ea..24cdd40f1 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -19,3 +19,11 @@ There are three projects:
 Each of these needs to have SV augmentation, and the best way to
 do it is if they are all done at the same time, implementing the same
 incremental feature.
+
+# Critical tasks
+
+These are prerequisite tasks:
+
+* power-gem5 automanagement, similar to pygdbmi for starting qemu
+* c++, c and python macros for generating [[sv/svp64]] assembler
+  (svp64 prefixes)