From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 12 Mar 2013 15:59:24 +0000 (+0100)
Subject: examples/pytholite: use new APIs
X-Git-Tag: 24jan2021_ls180~2099^2~650
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c99cc9343fc382d5be9ffe0da58de58c24c29670;p=litex.git

examples/pytholite: use new APIs
---

diff --git a/examples/pytholite/basic.py b/examples/pytholite/basic.py
index 97e20a1d..c1b4b780 100644
--- a/examples/pytholite/basic.py
+++ b/examples/pytholite/basic.py
@@ -17,8 +17,7 @@ def run_sim(ng):
 	g.add_connection(ng, d)
 	
 	c = CompositeActor(g)
-	fragment = c.get_fragment()
-	sim = Simulator(fragment)
+	sim = Simulator(c)
 	sim.run(30)
 	del sim
 
@@ -32,6 +31,6 @@ def main():
 	run_sim(ng_pytholite)
 	
 	print("Converting Pytholite to Verilog:")
-	print(verilog.convert(ng_pytholite.get_fragment()))
+	print(verilog.convert(ng_pytholite))
 
 main()
diff --git a/examples/pytholite/uio.py b/examples/pytholite/uio.py
index 01b52e11..9499200e 100644
--- a/examples/pytholite/uio.py
+++ b/examples/pytholite/uio.py
@@ -7,6 +7,7 @@ from migen.uio.ioo import UnifiedIOSimulation
 from migen.pytholite.transel import Register
 from migen.pytholite.compiler import make_pytholite
 from migen.sim.generic import Simulator
+from migen.fhdl.module import Module
 from migen.fhdl.specials import Memory
 from migen.fhdl import verilog
 
@@ -29,18 +30,18 @@ class SlaveModel(wishbone.TargetModel):
 	def read(self, address):
 		return address + 4
 
+class TestBench(Module):
+	def __init__(self, ng):
+		g = DataFlowGraph()
+		d = Dumper(layout)
+		g.add_connection(ng, d)
+		
+		self.submodules.slave = wishbone.Target(SlaveModel())
+		self.submodules.intercon = wishbone.InterconnectPointToPoint(ng.buses["wb"], self.slave.bus)
+		self.submodules.ca = CompositeActor(g)
+
 def run_sim(ng):
-	g = DataFlowGraph()
-	d = Dumper(layout)
-	g.add_connection(ng, d)
-	
-	slave = wishbone.Target(SlaveModel())
-	intercon = wishbone.InterconnectPointToPoint(ng.buses["wb"], slave.bus)
-	
-	c = CompositeActor(g)
-	fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment()
-	
-	sim = Simulator(fragment)
+	sim = Simulator(TestBench(ng))
 	sim.run(50)
 	del sim