From: Kyrylo Tkachov Date: Fri, 6 Nov 2015 12:04:15 +0000 (+0000) Subject: [ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulator forwar... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c9aa6b940fb8c010ffbba8a6a2eb3ce1de21389f;p=gcc.git [ARM/AArch64] PR 68088: Fix RTL checking ICE due to subregs inside accumulator forwarding check PR target/68088 * config/arm/aarch-common.c (aarch_accumulator_forwarding): Strip subregs from accumulator and make sure it's a register. * gcc.dg/pr68088_1.c: New test. From-SVN: r229845 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9adcd20d145..3966f515860 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-11-06 Kyrylo Tkachov + + PR target/68088 + * config/arm/aarch-common.c (aarch_accumulator_forwarding): Strip + subregs from accumulator and make sure it's a register. + 2015-11-06 Simon Dardis * config/mips/loongson.md (vec_loongson_extract_lo_): New, extract diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c index a940a0232f8..e6668d5742c 100644 --- a/gcc/config/arm/aarch-common.c +++ b/gcc/config/arm/aarch-common.c @@ -460,6 +460,12 @@ aarch_accumulator_forwarding (rtx_insn *producer, rtx_insn *consumer) return 0; } + if (GET_CODE (accumulator) == SUBREG) + accumulator = SUBREG_REG (accumulator); + + if (!REG_P (accumulator)) + return 0; + return (REGNO (dest) == REGNO (accumulator)); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3d1834dfb81..3bf8cf1bca0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-11-06 Kyrylo Tkachov + + PR target/68088 + * gcc.dg/pr68088_1.c: New test. + 2015-11-06 Richard Biener * gcc.dg/vect/bb-slp-38.c: New testcase. diff --git a/gcc/testsuite/gcc.dg/pr68088_1.c b/gcc/testsuite/gcc.dg/pr68088_1.c new file mode 100644 index 00000000000..49c6aa14543 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr68088_1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void bar (unsigned long); + +void +foo (unsigned long aul, unsigned m, unsigned i) +{ + while (1) + { + aul += i; + i = aul % m; + bar (aul); + } +}