From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 28 Feb 2019 17:32:29 +0000 (-0800)
Subject: synth_xilinx to now have shregmap call after dff2dffe
X-Git-Tag: yosys-0.9~171^2~71
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c9ab18889a63f74534c6fe9184ccb32e3661ab90;p=yosys.git

synth_xilinx to now have shregmap call after dff2dffe
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6c11d885d..afd868743 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -103,6 +103,7 @@ struct SynthXilinxPass : public Pass
 		log("        memory_map\n");
 		log("        dffsr2dff\n");
 		log("        dff2dffe\n");
+		log("        shregmap -init\n");
 		log("        opt -full\n");
 		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
 		log("        opt -fast\n");
@@ -222,6 +223,7 @@ struct SynthXilinxPass : public Pass
 			Pass::call(design, "memory_map");
 			Pass::call(design, "dffsr2dff");
 			Pass::call(design, "dff2dffe");
+			Pass::call(design, "shregmap -init");
 			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
 			Pass::call(design, "opt -fast");