From: Florent Kermarrec Date: Fri, 3 Apr 2015 10:45:32 +0000 (+0200) Subject: soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions X-Git-Tag: 24jan2021_ls180~2397 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c9c11e7aa837a266446cdaab5f869b7cfe1d2fac;p=litex.git soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions --- diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py index 441ad5e4..f900dac9 100644 --- a/misoclib/soc/__init__.py +++ b/misoclib/soc/__init__.py @@ -179,7 +179,7 @@ class SoC(Module): for name, csrs, mapaddr, rmap in self.csrbankarray.banks: self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, csrs) for name, memory, mapaddr, mmap in self.csrbankarray.srams: - self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, memory) + self.add_csr_region(name + "_" + memory.name_override, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, memory) # Interrupts if hasattr(self.cpu_or_bridge, "interrupt"):