From: Luke Kenneth Casson Leighton Date: Sun, 2 Jan 2022 23:29:00 +0000 (+0000) Subject: move linux kernel (dtbImage-microwatt) loading to 0x600000 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c9cf087ddd9d0d49bab1fa46af7657766d1c6eb2;p=microwatt.git move linux kernel (dtbImage-microwatt) loading to 0x600000 and it now works. takes about 2 hours to get to the login prompt, but it works. --- diff --git a/Makefile b/Makefile index 9ea90b5..820bd71 100644 --- a/Makefile +++ b/Makefile @@ -148,7 +148,7 @@ RAM_INIT_FILE=hello_world/hello_world.hex #MEMORY_SIZE=536870912 #RAM_INIT_FILE=dtbImage.microwatt.hex #SIM_MAIN_BRAM=false -#SIM_BRAM_CHAINBOOT=5242880 # 0x500000 +#SIM_BRAM_CHAINBOOT=6291456 # 0x600000 FPGA_TARGET ?= ORANGE-CRAB @@ -209,7 +209,7 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE) # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c - verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT --trace + verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT # --trace make -C obj_dir -f Vmicrowatt.mk @cp -f obj_dir/microwatt-verilator microwatt-verilator diff --git a/verilator/microwatt-verilator.cpp b/verilator/microwatt-verilator.cpp index 07320e9..f77b2c5 100644 --- a/verilator/microwatt-verilator.cpp +++ b/verilator/microwatt-verilator.cpp @@ -134,7 +134,7 @@ int main(int argc, char **argv) mem = _mem; size_t offs = 0x0; // normal start if (i == 2) { - offs = 0x500000; // hard-coded offset of the linux binary + offs = 0x600000; // hard-coded offset of the linux binary } printf("loading %s at 0x%x size 0x%x\n", bram_file, offs, statbuf.st_size);