From: lkcl Date: Sun, 26 Jun 2022 22:38:44 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~1505 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c9d911f920f8014d9631bb53cb8a32933045320a;p=libreriscv.git --- diff --git a/openpower/sv/svstep.mdwn b/openpower/sv/svstep.mdwn index 2eb9b7af3..ca29eebb7 100644 --- a/openpower/sv/svstep.mdwn +++ b/openpower/sv/svstep.mdwn @@ -34,6 +34,10 @@ state. If `SVi=0, Rc=0, vf=0` this instruction is a `nop`. When `SVi` is 1-4 the REMAP Schedule for a given SVSHAPE may be returned in `RT`. SVi=1 selects SVSHAPE0 current state, through to SVi=4 selects SVSHAPE3. +When `SVi` is 5, `SVSTATE.srcstep` is returned. +When `SVi` is 6, `SVSTATE.dststep` is returned. +As this is a Single-Predicated (1P) instruction, predication may be applied +to skip (or zero) elements. * Vertical-First Mode will return the current index (and move to the next state if `vf=1`) @@ -65,5 +69,6 @@ to achieve the exact same Schedule. It is evident however that before use some of the Indices may be arbitrarily altered as desired. `sv.svstep` helps the programmer avoid having to manually recreate Indices for certain -types of common Loop patterns, and in its simplest form, without REMAP, +types of common Loop patterns, and in its simplest form, without REMAP +(SVi=5 or SVi=6), is equivalent to the `iota` instruction found in other Vector ISAs*