From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Jul 2020 10:52:09 +0000 (+0100)
Subject: OP_RFID needs to read SRR0/1, OP_SC needs to write
X-Git-Tag: div_pipeline~162^2~72
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c9e99cb7b982228a7becde86d75070dc2574ebae;p=soc.git

OP_RFID needs to read SRR0/1, OP_SC needs to write
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 812bf72e..220b0e68 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -639,7 +639,9 @@ class PowerDecode2(Elaboratable):
             comb += e.traptype.eq(TT_ILLEG) # request illegal instruction
 
         # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
-        with m.If(e.insn_type == InternalOp.OP_TRAP):
+        # Note: OP_SC could actually be modified to just be a trap
+        with m.If((e.insn_type == InternalOp.OP_TRAP) |
+                  (e.insn_type == InternalOp.OP_SC)):
             # TRAP write fast1 = SRR0
             comb += e.write_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
             comb += e.write_fast1.ok.eq(1)
@@ -647,6 +649,16 @@ class PowerDecode2(Elaboratable):
             comb += e.write_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
             comb += e.write_fast2.ok.eq(1)
 
+        # RFID: needs to read SRR0/1
+        with m.If(e.insn_type == InternalOp.OP_RFID):
+            # TRAP read fast1 = SRR0
+            comb += e.read_fast1.data.eq(FastRegs.SRR0) # constant: SRR0
+            comb += e.read_fast1.ok.eq(1)
+            # TRAP read fast2 = SRR1
+            comb += e.read_fast2.data.eq(FastRegs.SRR1) # constant: SRR1
+            comb += e.read_fast2.ok.eq(1)
+
+
         return m
 
         # TODO: get msr, then can do privileged instruction