From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 3 Mar 2023 10:16:57 +0000 (+0000)
Subject: cleanup ls003 - clarify Rc=1 setting overflow,
X-Git-Tag: opf_rfc_ls001_v3~201
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c9eaf69b606abb36577889a8340e2bcec5883171;p=libreriscv.git

cleanup ls003 - clarify Rc=1 setting overflow,
remove comment on divmod2du, add pagebreaks
---

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index 2e231eafa..0ab082c0f 100644
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -247,9 +247,6 @@ maddedus r22,r6,r0,r3
 
 # Divide/Modulo Quad-Double Unsigned
 
-**Should name be Divide/Module Double Extended Unsigned?**
-**Check the pseudo-code comments**
-
 `divmod2du RT,RA,RB,RC`
 
 |  0-5  | 6-10 | 11-15 | 16-20 | 21-25 | 26-31 | Form    |
@@ -321,6 +318,9 @@ Examples:
 # ((r0 << 64) + r2) % r1, store in r2
 divmod2du r4, r0, r1, r2
 ```
+
+----------
+
 \newpage{}
 
 # Double-Shift Left Doubleword
@@ -349,20 +349,22 @@ Special Registers Altered:
 The contents of register RA are shifted left the number
 of bits specified by (RB) 58:63. The same number of
 shifted bits are taken from the **right** (LSB) end of register
-RC and placed into the *rightmost* (LSB) end of the result, RT.
+RC and placed into the **rightmost** (LSB) end of the result, RT.
 Additionally, the MSB (leftmost) bits of register RA that would normally
 be discarded by a 64-bit left shift are placed into the
 LSBs of RS.
 
-When Rc=1, and the value in RS is nonzero,
-the overflow flag is raised in CR0. All other bits of CR0
-are set to zero. XER.OV and XER.SO remain unchanged.
+When Rc=1, the overflow flag in CR0 is set if RS is nonzero,
+or cleared if it is zero; all other bits of CR0 are set from RT as normal. 
+XER.OV and XER.SO remain unchanged.
 
 *Programmer's note:
 similar to maddedu and divmod2du, dsld can be chained (using RC),
-effectively using RC as a 64-bit carry-in and carry-out.*
+effectively using RC as a 64-bit carry-in and carry-out. Arbitrary
+length Scalar-Vector shift may be performed without the additional
+masking instructions normally needed.*
 
-\newpage{}
+----------
 
 # Double-Shift Right Doubleword
 
@@ -389,19 +391,23 @@ Special Registers Altered:
 
 The contents of register RA are shifted right the number
 of bits specified by (RB) 58:63. The same number of
-shifted bits are taken from the **left** (LSB) end of register RC
-and placed into the MSBs of the result, RT.
+shifted bits are taken from the **left** (MSB) end of register RC
+and placed into the **leftmost** (MSB) end of the result, RT.
 Additionally, the LSB (rightmost) bits of register RA that would normally
 be discarded by a 64-bit right shift are placed into the
 MSBs of RS.
 
-When Rc=1, and the value in RS is nonzero,
-the overflow flag is raised in CR0. All other bits of CR0
-are set to zero. XER.OV and XER.SO remain unchanged.
+When Rc=1, the overflow flag in CR0 is set if RS is nonzero,
+or cleared if it is zero; all other bits of CR0 are set from RT as normal. 
+XER.OV and XER.SO remain unchanged.
 
 *Programmer's note:
 similar to maddedu and divmod2du, dsrd can be chained (using RC),
-effectively using RC as a 64-bit carry-in and carry-out.*
+effectively using RC as a 64-bit carry-in and carry-out. Arbitrary
+length Scalar-Vector shift may be performed without the additional
+masking instructions normally needed.*
+
+----------
 
 \newpage{}
 
@@ -449,6 +455,8 @@ XO (26:30)
     Formats: ... VA2, ...
 ```
 
+----------
+
 # Appendices
 
     Appendix E Power ISA sorted by opcode