From: Robert Jordens <jordens@gmail.com>
Date: Fri, 27 Feb 2015 03:19:39 +0000 (-0700)
Subject: gensoc: missing self.
X-Git-Tag: 24jan2021_ls180~2596
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c9ed38dec815d165404a386db35e420fb8ecabac;p=litex.git

gensoc: missing self.
---

diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py
index ae880529..46068ccc 100644
--- a/misoclib/gensoc/__init__.py
+++ b/misoclib/gensoc/__init__.py
@@ -193,7 +193,7 @@ class SDRAMSoC(GenSoC):
 				self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), sdramcon.bus)
 			elif (sdram_width < 32):
 				self.submodules.dc = wishbone.DownConverter(32, sdram_width)
-				self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, sdramcon.bus)
+				self.submodules.intercon = wishbone.InterconnectPointToPoint(self.dc.wishbone_o, sdramcon.bus)
 				self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.dc.wishbone_i)
 			else:
 				raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))