From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 27 Mar 2022 12:16:48 +0000 (+0100)
Subject: update hyperram image and add links to datasheet and model
X-Git-Tag: opf_rfc_ls005_v1~2976
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=c9f85739b3ec68f1fffab11b256cb34beb3b070f;p=libreriscv.git

update hyperram image and add links to datasheet and model
---

diff --git a/HDL_workflow/2022-03-22_15-56.png b/HDL_workflow/2022-03-22_15-56.png
index 80e32cda8..9cd7153d5 100644
Binary files a/HDL_workflow/2022-03-22_15-56.png and b/HDL_workflow/2022-03-22_15-56.png differ
diff --git a/HDL_workflow/HyperRAM.mdwn b/HDL_workflow/HyperRAM.mdwn
index 2e28269fd..d9fa06d7d 100644
--- a/HDL_workflow/HyperRAM.mdwn
+++ b/HDL_workflow/HyperRAM.mdwn
@@ -5,6 +5,10 @@
   be constructed and soldered
   <https://www.amazon.co.uk/HALJIA-2-54mm-Dupont-Jumper-Connectors/dp/B06WWB66WL/>
 * nmigen [hyperram.py](https://git.libre-soc.org/?p=lambdasoc.git;a=blob;f=lambdasoc/periph/hyperram.py;hb=HEAD) module
+* Winbond Datasheet for Quad 1bitsqared PMOD:
+  <https://ftp.libre-soc.org/W956x8MBYA_64Mb_HyperBus_pSRAM_TFBGA24_datasheet_A01-005_20211208.pdf>
+* Winbond Verilog Model for W956A8MBY:
+  <https://www.winbond.com/resource-files/W956x8MBY_verilog_p.zip>
 
 ```
 from nmigen.resources.memory import HyperRAMResources