From: Cesar Strauss <cestrauss@gmail.com>
Date: Sat, 6 Mar 2021 19:39:14 +0000 (-0300)
Subject: Enable the Simple-V loop test case
X-Git-Tag: convert-csv-opcode-to-binary~100
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca082b68683bff0934d917d2a16d278232300215;p=soc.git

Enable the Simple-V loop test case
---

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index 59b39db4..335e3bfd 100644
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -7,7 +7,6 @@ from soc.sv.trans.svp64 import SVP64Asm
 
 class SVP64ALUTestCase(TestAccumulatorBase):
 
-    @skip_case("VL hardware loop is not yet implemented")
     def case_1_sv_add(self):
         # adds:
         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234