From: lkcl <lkcl@web>
Date: Wed, 28 Sep 2022 01:10:35 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~275
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca29af1117e2ae633ef838a83f2cc3f402ceadb7;p=libreriscv.git

---

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index 472dfc6ff..44c0f7992 100644
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -888,8 +888,9 @@ the starting Vector point of the operation to the next register it
 can be seen that the offset of 0-7 would be sufficient.  Unfortunately
 however some operations are EXTRA2-encoded it is **not possible**
 to increase the GPR/FPR register number by one, because EXTRA2-encoding
-of GPR/FPR Vector numbers are restricted to even numbering. The
-additional offset range (8-15) helps overcome this limitation.*
+of GPR/FPR Vector numbers are restricted to even numbering.
+For CR Fields the EXTRA2 encoding is even more sparse.
+The additional offset range (8-15) helps overcome these limitations.*
 
 *Hardware Implementor's note: with the offsets only being immediates
 and with register numbering being entirely immediate as well it is