From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 1 Mar 2019 18:25:23 +0000 (+0100)
Subject: Fix ECP5 cells_sim for iverilog
X-Git-Tag: yosys-0.9~283^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca2b3feed82f923f06d0cf57787818f0f6793157;p=yosys.git

Fix ECP5 cells_sim for iverilog
---

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 8320ee70a..1e4002ee0 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -223,11 +223,12 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
+	wire srval;
 	generate
 		if (LSRMODE == "PRLD")
-			wire srval = M;
+			assign srval = M;
 		else
-			localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+			assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 	endgenerate
 
 	initial Q = srval;