From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 26 Mar 2022 21:36:59 +0000 (+0000)
Subject: add missing ECP5 model OBZ.v and rename testbench
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca32d906a8a6fbd7d98292749a6bc70970c72be8;p=ls2.git

add missing ECP5 model OBZ.v and rename testbench
---

diff --git a/runsimsoc_hyperram.sh b/runsimsoc_hyperram.sh
index 4e235d4..3bba16d 100755
--- a/runsimsoc_hyperram.sh
+++ b/runsimsoc_hyperram.sh
@@ -23,7 +23,7 @@ iverilog -Wall -g2012 -s simsoc_hyperram_tb -o simsoc \
     ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
 	${LIB_DIR}/FD1S3AX.v ${LIB_DIR}/SGSR.v ${LIB_DIR}/ODDRX2F.v \
     ${LIB_DIR}/ODDRX2DQA.v ${LIB_DIR}/DELAYF.v ${LIB_DIR}/BB.v \
-    ${LIB_DIR}/OB.v ${LIB_DIR}/IB.v \
+    ${LIB_DIR}/OB.v ${LIB_DIR}/IB.v ${LIB_DIR}/OBZ.v \
 	${LIB_DIR}/DQSBUFM.v ${LIB_DIR}/UDFDL5_UDP_X.v \
     ${LIB_DIR}/TSHX2DQSA.v ${LIB_DIR}/TSHX2DQA.v \
     ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v \
diff --git a/src/simsoc_hyperram_tb.v b/src/simsoc_hyperram_tb.v
index be28bd2..e19a4a0 100644
--- a/src/simsoc_hyperram_tb.v
+++ b/src/simsoc_hyperram_tb.v
@@ -3,7 +3,7 @@
 
 `timescale 1 ns / 1 ns
 
-module simsoctb;
+module simsoc_hyperram_tb;
   // GSR & PUR init requires for Lattice models
   GSR GSR_INST (
     .GSR(1'b1)