From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 17 Feb 2014 08:44:39 +0000 (+0100)
Subject: Better preserve wires when flattening (in comparison to techmap)
X-Git-Tag: yosys-0.3.0~141
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca53ef50982d84917a4f6d293dd0d07805bb8eb6;p=yosys.git

Better preserve wires when flattening (in comparison to techmap)
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index f0d1e6da4..53164b58a 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -151,18 +151,18 @@ struct TechmapWorker
 			if (c.second.width < c.first.width)
 				c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width));
 			assert(c.first.width == c.second.width);
-#if 0
-			// more conservative approach:
-			// connect internal and external wires
-			module->connections.push_back(c);
-#else
-			// approach that yields nicer outputs:
-			// replace internal wires that are connected to external wires
-			if (w->port_output)
-				port_signal_map.add(c.second, c.first);
-			else
-				port_signal_map.add(c.first, c.second);
-#endif
+			if (flatten_mode) {
+				// more conservative approach:
+				// connect internal and external wires
+				module->connections.push_back(c);
+			} else {
+				// approach that yields nicer outputs:
+				// replace internal wires that are connected to external wires
+				if (w->port_output)
+					port_signal_map.add(c.second, c.first);
+				else
+					port_signal_map.add(c.first, c.second);
+			}
 		}
 
 		for (auto &it : tpl->cells) {