From: lkcl <lkcl@web>
Date: Thu, 4 May 2023 18:33:59 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca5686284f66fe1726ec0d6cedfe9b6af9f21c43;p=libreriscv.git

---

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index 75cc582d2..9a09735ed 100644
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -276,22 +276,22 @@ For a separate source/dest SUBVL (again, no elwidth overrides):
         if outer:
             for j in range(dst_subvl):
                 for i in range(VL):
-                    ....
+                    yield j*VL+i
         else:
             for i in range(VL):
                 for j in range(dst_subvl):
-                    ....
+                    yield i*dst_subvl+j
 
     # yield an outer-SUBVL or inner VL loop with SUBVL
     def index_src(outer):
         if outer:
             for j in range(SUBVL):
                 for i in range(VL):
-                    ....
+                    yield j*VL+i
         else:
             for i in range(VL):
                 for j in range(SUBVL):
-                    ....
+                    yield i*SUBVL+j
 ```
 
 "yield" from python is used here for simplicity and clarity.