From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 1 Dec 2015 09:20:16 +0000 (+0100)
Subject: boards/targets: add default rom/ram configuration for arty
X-Git-Tag: 24jan2021_ls180~2030
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca6b9aa6e3b14929fe84ea9adbe59b45947b63d6;p=litex.git

boards/targets: add default rom/ram configuration for arty
---

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index eb07d1ae..35b67026 100644
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -72,7 +72,11 @@ class _CRG(Module):
 class BaseSoC(SoCCore):
     def __init__(self, **kwargs):
         platform = arty.Platform()
-        SoCCore.__init__(self, platform, clk_freq=100*1000000, **kwargs)
+        SoCCore.__init__(self, platform, clk_freq=100*1000000,
+                         integrated_rom_size=0x8000,
+                         integrated_sram_size=0x8000,
+                         integrated_main_ram_size=0x10000,
+                         **kwargs)
 
         self.submodules.crg = _CRG(platform)