From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 15 Sep 2022 20:48:28 +0000 (+0100)
Subject: add minor_4.csv for maddld/maddhdu/maddhd and to insn_db.csv
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca6d41b459a679c5cfa52bf99d4efc5b2c0ec3b4;p=openpower-isa.git

add minor_4.csv for maddld/maddhdu/maddhd and to insn_db.csv
also add test_pysvp64dis.py to check it asm/disasms
---

diff --git a/openpower/isatables/insndb.csv b/openpower/isatables/insndb.csv
index 4b71a074..80b483de 100644
--- a/openpower/isatables/insndb.csv
+++ b/openpower/isatables/insndb.csv
@@ -6,6 +6,7 @@ minor_58.csv,58,30:31,NONE,integer
 minor_62.csv,62,30:31,NONE,integer
 minor_22.csv,22,21:31,NONE,pattern
 minor_5.csv,5,21:31,NONE,pattern
+minor_4.csv,4,26:31,NONE,integer
 minor_63.csv,63,21:30,NONE,pattern
 minor_59.csv,59,21:30,NONE,pattern
 major.csv,NONE,0:5,NONE,integer
diff --git a/openpower/isatables/minor_4.csv b/openpower/isatables/minor_4.csv
new file mode 100644
index 00000000..b41cb203
--- /dev/null
+++ b/openpower/isatables/minor_4.csv
@@ -0,0 +1,6 @@
+# SPDX-License-Header: CC-BY-4
+# derived from microwatt decode1.vhdl, with thanks and gratitude (IBM, OPF)
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
+48,ALU,OP_MADDHD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddhd,VA,,1,
+49,ALU,OP_MADDHDU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddhdu,VA,,1,
+51,ALU,OP_MADDLD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddld,VA,,1,
diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 977ec7d6..6694fae0 100644
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -155,6 +155,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
+    def test_8_madd(self):
+        expected = [
+                    "maddhd 5,4,5,3",
+                    "maddhdu 5,4,5,3",
+                    "maddld 5,4,5,3",
+                        ]
+        self._do_tst(expected)
+
 if __name__ == "__main__":
     unittest.main()