From: lkcl <lkcl@web>
Date: Sat, 1 Apr 2023 19:52:38 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~192
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca7e3a518cdf448fee69af83a0232f6bfe1d0bad;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index d901a720a..d0c808437 100644
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -212,7 +212,7 @@ Performance designs.
 For a comparative data point the VSR Registers may be expressed in the
 same fashion. The c code below is directly an expression of Figure 97 in
 Power ISA Public v3.1 Book I Section 6.3 page 258, *after compensating for
-MSB0 numbering in both bits abd elements, adapting in full to LSB0 numbering,
+MSB0 numbering in both bits and elements, adapting in full to LSB0 numbering,
 and obeying LE ordering*.
 
 **Crucial to understanding why the subtraction from 1,3,7,15 is present