From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 11 Oct 2019 06:59:25 +0000 (+0200)
Subject: soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed)
X-Git-Tag: 24jan2021_ls180~917
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca81cc209b6782a34455addf517c2893ff8ffaf7;p=litex.git

soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed)
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 0284252f..eecfb54a 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -184,6 +184,12 @@ class SoCCore(Module):
 
             # Add CPU buses as Wisbone masters
             for bus in self.cpu.buses:
+                assert bus.data_width in [32, 64, 128]
+                # Down Convert CPU buses to 32-bit if needed
+                if bus.data_width != 32:
+                    dc_bus = wishbone.Interface()
+                    self.submodules += wishbone.Converter(bus, dc_bus)
+                    bus = dc_bus
                 self.add_wb_master(bus)
 
             # Add CPU CSR (dynamic)
diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index f76cdb4c..d32799b6 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -34,6 +34,8 @@ _layout = [
 
 class Interface(Record):
     def __init__(self, data_width=32, adr_width=30):
+        self.data_width = data_width
+        self.adr_width  = adr_width
         Record.__init__(self, set_layout_parameters(_layout,
             adr_width=adr_width,
             data_width=data_width,