From: Walfred Tedeschi Date: Tue, 3 Dec 2013 13:31:03 +0000 (+0000) Subject: Documentation for MPX. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca8941bbd088002cb8ff87abe16d02ecc8d58d1e;p=binutils-gdb.git Documentation for MPX. 2013-11-20 Walfred Tedeschi * NEWS: Add section for Intel(R) Architecture Instructions Extesions mentioning MPX. doc/ * gdb.texinfo (i386 Features): Add MPX feature registers. (x86 Specific featuresx86 Architecture-specific Issues): Adds a subsubsection for MPX and describes the display of the boundary registers. Signed-off-by: Walfred Tedeschi --- diff --git a/gdb/ChangeLog b/gdb/ChangeLog index cbf40398b93..22debbb1e4e 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2013-12-03 Walfred Tedeschi + + * NEWS: Add section for Intel(R) Architecture Instructions + Extesions mentioning MPX. + 2013-12-03 Joel Brobecker * ada-lex.l (find_dot_all): Use strncasecmp instead of strncmp. diff --git a/gdb/NEWS b/gdb/NEWS index a8ae8c7b7a5..ae84e009b80 100644 --- a/gdb/NEWS +++ b/gdb/NEWS @@ -5577,3 +5577,5 @@ GDB now handles cross debugging. If you are remotely debugging between two different machines, type ``./configure host -target=targ''. Host is the machine where GDB will run; targ is the machine where the program that you are debugging will run. + + * GDB now supports access to Intel(R) MPX registers on GNU/Linux. diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog index 4080bb957c1..e925da1dd15 100644 --- a/gdb/doc/ChangeLog +++ b/gdb/doc/ChangeLog @@ -1,3 +1,10 @@ +2013-12-03 Walfred Tedeschi + + * gdb.texinfo (i386 Features): Add MPX feature registers. + (x86 Specific featuresx86 Architecture-specific Issues): Adds + a subsubsection for MPX and describes the display of the + boundary registers. + 2013-12-03 Joel Brobecker * gdb.texinfo (GDB/MI Miscellaneous Commands): Remove the diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index 2602427fb19..5896e3a61e1 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -21376,6 +21376,39 @@ be returned in a register. @kindex show struct-convention Show the current setting of the convention to return @code{struct}s from functions. + +@cindex Intel(R) Memory Protection Extensions (MPX). +@subsubsection Intel(R) @dfn{Memory Protection Extensions} (MPX). + +@item bnd0raw..bnd3raw and bnd0@dots{}bnd3 registers display. +Memory Protection Extension (MPX) adds the bound registers @samp{BND0} +@footnote{The register named with capital letters represent the architecture +registers.} through @samp{BND3}. Bound registers store a pair of 64-bit values +which are the lower bound and upper bound. Bounds are effective addresses or +memory locations. The upper bounds are architecturally represented in 1's +complement form. A bound having lower bound = 0, and upper bound = 0 +(1's complement of all bits set) will allow access to the entire address space. + +@samp{BND0} through @samp{BND3} are represented in @value{GDBN} as @samp{bnd0raw} +through @samp{bnd3raw}. Pseudo registers @samp{bnd0} through @samp{bnd3} +display the upper bound performing the complement of one operation on the +upper bound value, i.e.@ when upper bound in @samp{bnd0raw} is 0 in the +@value{GDBN} @samp{bnd0} it will be @code{0xfff@dots{}}. In this sense it +can also be noted that the upper bounds are inclusive. + +As an example, assume that the register BND0 holds bounds for a pointer having +access allowed for the range between 0x32 and 0x71. The values present on +bnd0raw and bnd registers are presented as follows: + +@smallexample + bnd0raw = @{0x32, 0xffffffff8e@} + bnd0 = @{lbound = 0x32, ubound = 0x71@} : size 64 +@end smallexample + +This way the raw value can be accessed via bnd0raw@dots{}bnd3raw. Any change +on bnd0@dots{}bnd3 or bnd0raw@dots{}bnd3raw is reflect on its counterpart. When the +bnd0@dots{}bnd3 registers are displayed via Python, the display includes the memory size, +in bits, accessible to the pointer. @end table @node Alpha @@ -43226,6 +43259,16 @@ describe the upper 128 bits of @sc{ymm} registers: @samp{ymm0h} through @samp{ymm15h} for amd64 @end itemize +The @samp{org.gnu.gdb.i386.mpx} is an optional feature representing Intel(R) +Memory Protection Extension (MPX). It should describe the following registers: + +@itemize @minus +@item +@samp{bnd0raw} through @samp{bnd3raw} for i386 and amd64. +@item +@samp{bndcfgu} and @samp{bndstatus} for i386 and amd64. +@end itemize + The @samp{org.gnu.gdb.i386.linux} feature is optional. It should describe a single register, @samp{orig_eax}.