From: Piotr Binkowski <pbinkowski@antmicro.com>
Date: Wed, 20 May 2020 11:35:18 +0000 (+0200)
Subject: software/bios/isr: add support for cv32e40p
X-Git-Tag: 24jan2021_ls180~303^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca8cb834245929769d947ab25b9daab2aa9a88ce;p=litex.git

software/bios/isr: add support for cv32e40p
---

diff --git a/litex/soc/software/bios/isr.c b/litex/soc/software/bios/isr.c
index 0044f3d1..dafa2c18 100644
--- a/litex/soc/software/bios/isr.c
+++ b/litex/soc/software/bios/isr.c
@@ -62,6 +62,41 @@ void isr(void)
 		*((unsigned int *)PLIC_CLAIM) = claim;
 	}
 }
+#elif defined(__cv32e40p__)
+
+#define FIRQ_OFFSET 16
+#define IRQ_MASK 0x7FFFFFFF
+#define INVINST 2
+#define ECALL 11
+#define RISCV_TEST
+
+void isr(void)
+{
+    unsigned int cause = csrr(mcause) & IRQ_MASK;
+
+    if (csrr(mcause) & 0x80000000) {
+#ifndef UART_POLLING
+        if (cause == (UART_INTERRUPT+FIRQ_OFFSET)){
+            uart_isr();
+        }
+#endif
+    } else {
+#ifdef RISCV_TEST
+        int gp;
+        asm volatile ("mv %0, gp" : "=r"(gp));
+        printf("E %d\n", cause);
+        if (cause == INVINST) {
+            printf("Inv Instr\n");
+            for(;;);
+        }
+        if (cause == ECALL) {
+            printf("Ecall (gp: %d)\n", gp);
+            csrw(mepc, csrr(mepc)+4);
+        }
+#endif
+    }
+}
+
 #else
 void isr(void)
 {