From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 20 Jun 2022 17:42:26 +0000 (+0100)
Subject: add absolute-signed-diff next to absolute-unsigned-diff
X-Git-Tag: sv_maxu_works-initial~373
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca9acfa997a9e771e24937b6a7ee1e1e43ce06e8;p=openpower-isa.git

add absolute-signed-diff next to absolute-unsigned-diff
---

diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn
index 3c89b569..2498163c 100644
--- a/openpower/isa/av.mdwn
+++ b/openpower/isa/av.mdwn
@@ -86,6 +86,22 @@ Special Registers Altered:
 
     CR0                     (if Rc=1)
 
+# DRAFT Absolute Signed Difference
+
+X-Form
+
+* absds  RT,RA,RB (Rc=0)
+* absds. RT,RA,RB (Rc=1)
+
+Pseudo-code:
+
+    if (RA) < (RB) then RT <- ¬(RA) + (RB) + 1
+    else                RT <- ¬(RB) + (RA) + 1
+
+Special Registers Altered:
+
+    CR0                     (if Rc=1)
+
 # DRAFT Absolute Unsigned Difference
 
 X-Form
@@ -95,7 +111,7 @@ X-Form
 
 Pseudo-code:
 
-    if (RA) < (RB) then RT <- ¬(RA) + (RB) + 1
+    if (RA) <u (RB) then RT <- ¬(RA) + (RB) + 1
     else                RT <- ¬(RB) + (RA) + 1
 
 Special Registers Altered:
diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index 84373194..da486736 100644
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -9,5 +9,6 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0001001110-,ALU,OP_MINMAX,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,minu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1101001110-,ALU,OP_AVGADD,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,avgadd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1011110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absdu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+1001110110-,ALU,OP_ABSDIFF,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absds,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absdacu,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 0111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absdacs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index f3a51a89..7b8224e4 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1284,6 +1284,11 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
             illegal = False
             ins_name = asmop
 
+        # and anything absds
+        if asmop.startswith('absds'):
+            illegal = False
+            ins_name = asmop
+
         # and anything absadd
         if asmop.startswith('absdac'):
             illegal = False
diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index e72328c9..a9584dd5 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -260,7 +260,7 @@ _insns = [
     "addg6s",
     "and", "andc", "andi.", "andis.",
     "attn",
-    "absdu",                                  # AV bitmanip
+    "absdu", "absds",                         # AV bitmanip
     "absdacs", "absdacu",                     # AV bitmanip
     "avgadd",                                 # AV bitmanip
     "b", "bc", "bcctr", "bclr", "bctar",
diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index f2ec28cb..f7bed852 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -443,9 +443,11 @@ class SVP64Asm:
 
         # and avgadd, absdu, absdacu, absdacs
         # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
-        if opcode in ['avgadd', 'absdu', 'absdacu', 'absdacs']:
+        if opcode in ['avgadd', 'absdu', 'absds', 'absdacu', 'absdacs']:
             if opcode[:5] == 'absdu':
                 XO = 0b1011110110
+            elif opcode[:5] == 'absds':
+                XO = 0b1001110110
             elif opcode[:6] == 'avgadd':
                 XO = 0b1101001110
             elif opcode[:7] == 'absdacu':
@@ -1339,6 +1341,7 @@ if __name__ == '__main__':
         'maxs. 3,12,5',
         'avgadd 3,12,5',
         'absdu 3,12,5',
+        'absds 3,12,5',
         'absdacu 3,12,5',
         'absdacs 3,12,5',
     ]
diff --git a/src/openpower/test/bitmanip/av_cases.py b/src/openpower/test/bitmanip/av_cases.py
index a48694de..292797a3 100644
--- a/src/openpower/test/bitmanip/av_cases.py
+++ b/src/openpower/test/bitmanip/av_cases.py
@@ -221,6 +221,32 @@ class AVTestCase(TestAccumulatorBase):
         e.intregs[3] = 0xffffffffffffffff
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
+    def case_0_absds(self):
+        lst = ["absds 3, 1, 2"]
+        lst = list(SVP64Asm(lst, bigendian))
+
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x1
+        initial_regs[2] = 0x2
+        e = ExpectedState(pc=4)
+        e.intregs[1] = 0x1
+        e.intregs[2] = 0x2
+        e.intregs[3] = 0x1
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
+    def case_1_absds(self):
+        lst = ["absds 3, 1, 2"]
+        lst = list(SVP64Asm(lst, bigendian))
+
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffffffffff
+        initial_regs[2] = 0x2
+        e = ExpectedState(pc=4)
+        e.intregs[1] = 0xffffffffffffffff
+        e.intregs[2] = 0x2
+        e.intregs[3] = 0x3
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
     def case_0_absdu(self):
         lst = ["absdu 3, 1, 2"]
         lst = list(SVP64Asm(lst, bigendian))
@@ -244,7 +270,7 @@ class AVTestCase(TestAccumulatorBase):
         e = ExpectedState(pc=4)
         e.intregs[1] = 0xffffffffffffffff
         e.intregs[2] = 0x2
-        e.intregs[3] = 0x3
+        e.intregs[3] = 0xfffffffffffffffd
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_2_absdu(self):
@@ -257,7 +283,7 @@ class AVTestCase(TestAccumulatorBase):
         e = ExpectedState(pc=4)
         e.intregs[1] = 0x2
         e.intregs[2] = 0xffffffffffffffff
-        e.intregs[3] = 0x3
+        e.intregs[3] = 0xfffffffffffffffd
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
     def case_0_absdacu(self):