From: Alexander Ivchenko Date: Wed, 27 Aug 2014 11:31:51 +0000 (+0000) Subject: sse.md (define_mode_iterator VI48_AVX512VL): New. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca9b264e415ca13cc4ff1b3ef93926b062ef6ab1;p=gcc.git sse.md (define_mode_iterator VI48_AVX512VL): New. gcc/ * config/i386/sse.md (define_mode_iterator VI48_AVX512VL): New. (define_mode_iterator VI_UNALIGNED_LOADSTORE): Delete. (define_mode_iterator VI_ULOADSTORE_BW_AVX512VL): New. (define_mode_iterator VI_ULOADSTORE_F_AVX512VL): Ditto. (define_expand "_loaddqu" with VI1): Change mode iterator. (define_expand "_loaddqu" with VI_ULOADSTORE_BW_AVX512VL): New. (define_expand "_loaddqu" with VI_ULOADSTORE_F_AVX512VL): Ditto. (define_insn "*_loaddqu" with VI1): Change mode iterator. (define_insn "*_loaddqu" with VI_ULOADSTORE_BW_AVX512VL): New. (define_insn "*_loaddqu" with VI_ULOADSTORE_F_AVX512VL): Ditto. (define_insn "_storedqu with VI1): Change mode iterator. (define_insn "_storedqu with VI_ULOADSTORE_BW_AVX512VL): New. (define_insn "_storedqu with VI_ULOADSTORE_BW_AVX512VL): Ditto. (define_insn "avx512f_storedqu_mask"): Delete. (define_insn "_storedqu_mask" with VI48_AVX512VL): New. (define_insn "_storedqu_mask" with VI12_AVX512VL): Ditto. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin From-SVN: r214570 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ded0288c082..5ccfd6e206e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,41 @@ +2014-08-27 Alexander Ivchenko + Maxim Kuznetsov + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/sse.md + (define_mode_iterator VI48_AVX512VL): New. + (define_mode_iterator VI_UNALIGNED_LOADSTORE): Delete. + (define_mode_iterator VI_ULOADSTORE_BW_AVX512VL): New. + (define_mode_iterator VI_ULOADSTORE_F_AVX512VL): Ditto. + (define_expand "_loaddqu" + with VI1): Change mode iterator. + (define_expand "_loaddqu" + with VI_ULOADSTORE_BW_AVX512VL): New. + (define_expand "_loaddqu" + with VI_ULOADSTORE_F_AVX512VL): Ditto. + (define_insn "*_loaddqu" + with VI1): Change mode iterator. + (define_insn "*_loaddqu" + with VI_ULOADSTORE_BW_AVX512VL): New. + (define_insn "*_loaddqu" + with VI_ULOADSTORE_F_AVX512VL): Ditto. + (define_insn "_storedqu + with VI1): Change mode iterator. + (define_insn "_storedqu + with VI_ULOADSTORE_BW_AVX512VL): New. + (define_insn "_storedqu + with VI_ULOADSTORE_BW_AVX512VL): Ditto. + (define_insn "avx512f_storedqu_mask"): Delete. + (define_insn "_storedqu_mask" with + VI48_AVX512VL): New. + (define_insn "_storedqu_mask" with + VI12_AVX512VL): Ditto. + 2014-08-27 Alexander Ivchenko Maxim Kuznetsov Anna Tikhonova diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index cd0c08e77b6..2fac897fb4d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -235,6 +235,10 @@ (define_mode_iterator VF_512 [V16SF V8DF]) +(define_mode_iterator VI48_AVX512VL + [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) + (define_mode_iterator VF2_AVX512VL [V8DF (V4DF "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")]) @@ -259,9 +263,13 @@ (define_mode_iterator VI1 [(V32QI "TARGET_AVX") V16QI]) -(define_mode_iterator VI_UNALIGNED_LOADSTORE - [(V32QI "TARGET_AVX") V16QI - (V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F")]) +(define_mode_iterator VI_ULOADSTORE_BW_AVX512VL + [V64QI + V32HI (V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL")]) + +(define_mode_iterator VI_ULOADSTORE_F_AVX512VL + [V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) ;; All DImode vector integer modes (define_mode_iterator VI8 @@ -1167,18 +1175,18 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) +/* For AVX, normal *mov_internal pattern will handle unaligned loads + just fine if misaligned_operand is true, and without the UNSPEC it can + be combined with arithmetic instructions. If misaligned_operand is + false, still emit UNSPEC_LOADU insn to honor user's request for + misaligned load. */ (define_expand "_loaddqu" - [(set (match_operand:VI_UNALIGNED_LOADSTORE 0 "register_operand") - (unspec:VI_UNALIGNED_LOADSTORE - [(match_operand:VI_UNALIGNED_LOADSTORE 1 "nonimmediate_operand")] + [(set (match_operand:VI1 0 "register_operand") + (unspec:VI1 + [(match_operand:VI1 1 "nonimmediate_operand")] UNSPEC_LOADU))] - "TARGET_SSE2 && " + "TARGET_SSE2 && && " { - /* For AVX, normal *mov_internal pattern will handle unaligned loads - just fine if misaligned_operand is true, and without the UNSPEC it can - be combined with arithmetic instructions. If misaligned_operand is - false, still emit UNSPEC_LOADU insn to honor user's request for - misaligned load. */ if (TARGET_AVX && misaligned_operand (operands[1], mode)) { @@ -1192,25 +1200,61 @@ } }) +(define_expand "_loaddqu" + [(set (match_operand:VI_ULOADSTORE_BW_AVX512VL 0 "register_operand") + (unspec:VI_ULOADSTORE_BW_AVX512VL + [(match_operand:VI_ULOADSTORE_BW_AVX512VL 1 "nonimmediate_operand")] + UNSPEC_LOADU))] + "TARGET_AVX512BW" +{ + if (misaligned_operand (operands[1], mode)) + { + rtx src = operands[1]; + if () + src = gen_rtx_VEC_MERGE (mode, operands[1], + operands[2 * ], + operands[3 * ]); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], src)); + DONE; + } +}) + +(define_expand "_loaddqu" + [(set (match_operand:VI_ULOADSTORE_F_AVX512VL 0 "register_operand") + (unspec:VI_ULOADSTORE_F_AVX512VL + [(match_operand:VI_ULOADSTORE_F_AVX512VL 1 "nonimmediate_operand")] + UNSPEC_LOADU))] + "TARGET_AVX512F" +{ + if (misaligned_operand (operands[1], mode)) + { + rtx src = operands[1]; + if () + src = gen_rtx_VEC_MERGE (mode, operands[1], + operands[2 * ], + operands[3 * ]); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], src)); + DONE; + } +}) + (define_insn "*_loaddqu" - [(set (match_operand:VI_UNALIGNED_LOADSTORE 0 "register_operand" "=v") - (unspec:VI_UNALIGNED_LOADSTORE - [(match_operand:VI_UNALIGNED_LOADSTORE 1 "nonimmediate_operand" "vm")] + [(set (match_operand:VI1 0 "register_operand" "=v") + (unspec:VI1 + [(match_operand:VI1 1 "nonimmediate_operand" "vm")] UNSPEC_LOADU))] - "TARGET_SSE2 && " + "TARGET_SSE2 && && " { switch (get_attr_mode (insn)) { case MODE_V8SF: case MODE_V4SF: return "%vmovups\t{%1, %0|%0, %1}"; - case MODE_XI: - if (mode == V8DImode) - return "vmovdqu64\t{%1, %0|%0, %1}"; - else - return "vmovdqu32\t{%1, %0|%0, %1}"; default: - return "%vmovdqu\t{%1, %0|%0, %1}"; + if (!(TARGET_AVX512VL && TARGET_AVX512BW)) + return "%vmovdqu\t{%1, %0|%0, %1}"; + else + return "vmovdqu\t{%1, %0|%0, %1}"; } } [(set_attr "type" "ssemov") @@ -1233,10 +1277,34 @@ ] (const_string "")))]) +(define_insn "*_loaddqu" + [(set (match_operand:VI_ULOADSTORE_BW_AVX512VL 0 "register_operand" "=v") + (unspec:VI_ULOADSTORE_BW_AVX512VL + [(match_operand:VI_ULOADSTORE_BW_AVX512VL 1 "nonimmediate_operand" "vm")] + UNSPEC_LOADU))] + "TARGET_AVX512BW" + "vmovdqu\t{%1, %0|%0, %1}"; + [(set_attr "type" "ssemov") + (set_attr "movu" "1") + (set_attr "ssememalign" "8") + (set_attr "prefix" "maybe_evex")]) + +(define_insn "*_loaddqu" + [(set (match_operand:VI_ULOADSTORE_F_AVX512VL 0 "register_operand" "=v") + (unspec:VI_ULOADSTORE_F_AVX512VL + [(match_operand:VI_ULOADSTORE_F_AVX512VL 1 "nonimmediate_operand" "vm")] + UNSPEC_LOADU))] + "TARGET_AVX512F" + "vmovdqu\t{%1, %0|%0, %1}"; + [(set_attr "type" "ssemov") + (set_attr "movu" "1") + (set_attr "ssememalign" "8") + (set_attr "prefix" "maybe_evex")]) + (define_insn "_storedqu" - [(set (match_operand:VI_UNALIGNED_LOADSTORE 0 "memory_operand" "=m") - (unspec:VI_UNALIGNED_LOADSTORE - [(match_operand:VI_UNALIGNED_LOADSTORE 1 "register_operand" "v")] + [(set (match_operand:VI1 0 "memory_operand" "=m") + (unspec:VI1 + [(match_operand:VI1 1 "register_operand" "v")] UNSPEC_STOREU))] "TARGET_SSE2" { @@ -1246,13 +1314,16 @@ case MODE_V8SF: case MODE_V4SF: return "%vmovups\t{%1, %0|%0, %1}"; - case MODE_XI: - if (mode == V8DImode) - return "vmovdqu64\t{%1, %0|%0, %1}"; - else - return "vmovdqu32\t{%1, %0|%0, %1}"; default: - return "%vmovdqu\t{%1, %0|%0, %1}"; + switch (mode) + { + case V32QImode: + case V16QImode: + if (!(TARGET_AVX512VL && TARGET_AVX512BW)) + return "%vmovdqu\t{%1, %0|%0, %1}"; + default: + return "vmovdqu\t{%1, %0|%0, %1}"; + } } } [(set_attr "type" "ssemov") @@ -1276,21 +1347,56 @@ ] (const_string "")))]) -(define_insn "avx512f_storedqu_mask" - [(set (match_operand:VI48_512 0 "memory_operand" "=m") - (vec_merge:VI48_512 - (unspec:VI48_512 - [(match_operand:VI48_512 1 "register_operand" "v")] +(define_insn "_storedqu" + [(set (match_operand:VI_ULOADSTORE_BW_AVX512VL 0 "memory_operand" "=m") + (unspec:VI_ULOADSTORE_BW_AVX512VL + [(match_operand:VI_ULOADSTORE_BW_AVX512VL 1 "register_operand" "v")] + UNSPEC_STOREU))] + "TARGET_AVX512BW" + "vmovdqu\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "movu" "1") + (set_attr "ssememalign" "8") + (set_attr "prefix" "maybe_evex")]) + +(define_insn "_storedqu" + [(set (match_operand:VI_ULOADSTORE_F_AVX512VL 0 "memory_operand" "=m") + (unspec:VI_ULOADSTORE_F_AVX512VL + [(match_operand:VI_ULOADSTORE_F_AVX512VL 1 "register_operand" "v")] + UNSPEC_STOREU))] + "TARGET_AVX512F" + "vmovdqu\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "movu" "1") + (set_attr "ssememalign" "8") + (set_attr "prefix" "maybe_vex")]) + +(define_insn "_storedqu_mask" + [(set (match_operand:VI48_AVX512VL 0 "memory_operand" "=m") + (vec_merge:VI48_AVX512VL + (unspec:VI48_AVX512VL + [(match_operand:VI48_AVX512VL 1 "register_operand" "v")] UNSPEC_STOREU) (match_dup 0) (match_operand: 2 "register_operand" "Yk")))] "TARGET_AVX512F" -{ - if (mode == V8DImode) - return "vmovdqu64\t{%1, %0%{%2%}|%0%{%2%}, %1}"; - else - return "vmovdqu32\t{%1, %0%{%2%}|%0%{%2%}, %1}"; -} + "vmovdqu\t{%1, %0%{%2%}|%0%{%2%}, %1}" + [(set_attr "type" "ssemov") + (set_attr "movu" "1") + (set_attr "memory" "store") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "_storedqu_mask" + [(set (match_operand:VI12_AVX512VL 0 "memory_operand" "=m") + (vec_merge:VI12_AVX512VL + (unspec:VI12_AVX512VL + [(match_operand:VI12_AVX512VL 1 "register_operand" "v")] + UNSPEC_STOREU) + (match_dup 0) + (match_operand: 2 "register_operand" "Yk")))] + "TARGET_AVX512BW" + "vmovdqu\t{%1, %0%{%2%}|%0%{%2%}, %1}" [(set_attr "type" "ssemov") (set_attr "movu" "1") (set_attr "memory" "store")