From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 24 May 2021 17:05:10 +0000 (+0100)
Subject: change name of submodule to real_pll
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ca9cae263408f03d3368d9e93634e5484b17d87f;p=soc.git

change name of submodule to real_pll
---

diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py
index f8eb0abb..fd437ef1 100644
--- a/src/soc/clock/dummypll.py
+++ b/src/soc/clock/dummypll.py
@@ -25,13 +25,13 @@ class DummyPLL(Elaboratable):
                                   o_div_out_test=self.pll_test_o,
                                   o_vco_test_ana=self.pll_vco_o,
                            )
-            m.submodules['pll'] = pll
+            m.submodules['real_pll'] = pll
             #pll.attrs['blackbox'] = 1
         else:
             m.d.comb += self.clk_pll_o.eq(self.clk_24_i) # just pass through
             # just get something, stops yosys destroying (optimising) these out
             with m.If(self.clk_sel_i == 0):
-                m.d.comb += self.pll_ana_o.eq(self.clk_24_i)
+                m.d.comb += self.pll_test_o.eq(self.clk_24_i)
                 m.d.comb += self.pll_vco_o.eq(~self.clk_24_i)
 
 
diff --git a/src/soc/litex/florent b/src/soc/litex/florent
index e4ffa78b..67063859 160000
--- a/src/soc/litex/florent
+++ b/src/soc/litex/florent
@@ -1 +1 @@
-Subproject commit e4ffa78b6ca6cc9ed8d0407c4a73394991003663
+Subproject commit 670638591d786b042f85f3839c59eb92e34ba1e6