From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 20:47:47 +0000 (-0700)
Subject: Get wire via SigBit
X-Git-Tag: working-ls180~1085^2~83
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cab2bd083ed25ebe1113d5fd054df5983e5086e7;p=yosys.git

Get wire via SigBit
---

diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
index cd7461052..69a9c7af2 100644
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -11,7 +11,7 @@ endcode
 match first
 	select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
 	select !first->get_bool_attribute(\keep)
-	select !port(first, \Q).as_wire()->get_bool_attribute(\keep)
+	select !port(first, \Q)[0].wire->get_bool_attribute(\keep)
 	filter !non_first_cells.count(first)
 //generate
 //	SigSpec A = module->addWire(NEW_ID);
@@ -49,13 +49,13 @@ subpattern setup
 match first
 	select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
 	select !first->get_bool_attribute(\keep)
-	select !port(first, \Q).as_wire()->get_bool_attribute(\keep)
+	select !port(first, \Q)[0].wire->get_bool_attribute(\keep)
 endmatch
 
 match next
 	select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
 	select !next->get_bool_attribute(\keep)
-	select !port(next, \Q).as_wire()->get_bool_attribute(\keep)
+	select !port(next, \Q)[0].wire->get_bool_attribute(\keep)
 	select nusers(port(next, \Q)) == 2
 	index <IdString> next->type === first->type
 	index <SigSpec> port(next, \Q) === port(first, \D)
@@ -74,7 +74,7 @@ match next
 	semioptional
 	select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
 	select !next->get_bool_attribute(\keep)
-	select !port(next, \Q).as_wire()->get_bool_attribute(\keep)
+	select !port(next, \Q)[0].wire->get_bool_attribute(\keep)
 	select nusers(port(next, \Q)) == 2
 	index <IdString> next->type === chain.back()->type
 	index <SigSpec> port(next, \Q) === port(chain.back(), \D)