From: lkcl <lkcl@web>
Date: Sat, 16 Apr 2022 17:29:07 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2768
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=cab428c16335c6adac574fd7fce729ee354342dd;p=libreriscv.git

---

diff --git a/HDL_workflow/ls2.mdwn b/HDL_workflow/ls2.mdwn
index 68e61ccf0..ec647175a 100644
--- a/HDL_workflow/ls2.mdwn
+++ b/HDL_workflow/ls2.mdwn
@@ -56,3 +56,19 @@ If needed modify sources to produce a fixed file bitstream and
     minicom -D /dev/ttyUSB1
     xc3sprog -c nexys4 top.bit
 
+# Using ls2 with microwatt
+
+This is doable but tricky.  An older version is required at present.
+
+    git clone https://git.libre-soc.org/git/microwatt.git
+    git checkout microwatt_verilator
+    make microwatt.v
+
+From there, some hand-editing is required.  search for core_NNNNNNN_XXX_YYY
+and rename it to external_core_top. Save the file as external_core_top.v
+and it can be used in place of the Libre-SOC Core, above.
+
+In fact any core can be used with ls, as long as it is compliant with
+the interfaces.  Both Wishbone Interfaces must be WB4 Pipeline
+compliant (proper stall handling) or the stall signal faked externally
+with a wrapper: `stall=stb&~ack`